CMOS imaging device having optimized shape, and method for producing such a device by means of photocomposition

Patent metadata

Field	Value
Publication number	US-9385149-B2
Application number	US-201314412619-A
Country	US
Kind code	B2
Filing date	Jul 5, 2013
Priority date	Jul 5, 2012
Publication date	Jul 5, 2016
Grant date	Jul 5, 2016

Abstract

An imaging device comprises a sensor of surface area of at least 10 cm 2 and comprising: an image zone produced on a single substrate and comprising a group of pixels disposed in rows and columns, the number of pixels per column not being uniform for all the columns of pixels, each pixel collecting electric charges generated by a photosensitive element, row conductors linking the pixels row by row, column conductors linking the pixels column by column, row addressing blocks linked to the row conductors to address each row of pixels individually, and column reading blocks linked to the column conductors to read the electric charges collected by the pixels of the row selected by the row addressing blocks, the column reading blocks being situated at the periphery of the image zone; the row addressing blocks and the column reading blocks being produced on the same substrate as the image zone.

First claim

The invention claimed is:

1. A method for producing by photolithography an imaging device on a semi-conducting wafer having forming a substrate and an image zone produced on the substrate with a group of pixels disposed in rows and columns, the number of pixels per column not being uniform for all the columns of pixels, where each pixel has a charge collector element collecting electric charges generated as a function of a photon radiation received by the imaging device, with row conductors (Xi, XRAZi) linking the pixels row by row, column conductors (Yj) linking the pixels column by column, and row addressing blocks linked to the row conductors (Xi, XRAZi) to address each row of pixels individually, and column reading blocks linked to the column conductors (Yj) to read the electric charges collected by the pixels of the row selected by the row addressing blocks, the column reading blocks being situated at the periphery of the image zone, the row addressing blocks and the column reading blocks being produced on the same substrate as the image zone;
the method comprising a step in which a surface of the semi-conducting wafer is exposed zone by zone to a radiation through at least two sets of masks; each set of masks comprising several masks; each mask of one and the same set of masks including several regions, each region corresponding to a particular pattern; the at least two mask sets being configured to be able to produce, by photolithography, various patterns on the surface of the semi-conducting wafer; the image zone being obtained by the successive production of patterns, adjacent to one another, on the surface of the semi-conducting wafer; the image zone thus obtained exhibiting a surface area of greater than or equal to 10 cm 2 ;
wherein the number of patterns implemented is strictly greater than 1 and less than 15.

2. The method as claimed in claim 1 , in which each mask of the at least two sets of masks comprises n distinct regions, allowing respectively the production, by photolithography, of n patterns; n being an integer lying between 1 and 15.

3. The method as claimed in claim 1 , in which the number of patterns implemented is less than 8.

4. The method as claimed in claim 1 , in which the image zone is obtained by the production of patterns formed by means of two or three sets of masks.

5. The method as claimed in claim 1 , in which the peripheral pixels of the image zone form substantially a polygon comprising at least 5 sides.

6. The method as claimed in claim 1 , in which the peripheral pixels of the image zone form substantially a polygon comprising a number less than 20 of sides.

7. The method as claimed in claim 1 , in which the peripheral pixels of the image zone form substantially a regular octagon.

8. The method as claimed in claim 1 , in which each row addressing block is formed by the production of a pattern comprising a region corresponding to said row addressing block, at least one of the patterns forming a row addressing block exhibiting shapes inclined with respect to the rows and to the columns of pixels.

9. The method as claimed in claim 1 , in which each column reading block is formed by the production of a pattern comprising a region corresponding to said block, at least one of the patterns forming a column reading block exhibiting shapes inclined with respect to the rows and to the columns of pixels.

10. The method as claimed in claim 1 , in which the set or sets of masks are of rectangular shape, each pattern to be produced on the semi-conducting wafer being selected by one or more obturation flaps.

11. The method as claimed in claim 1 , in which the surface of the semi-conducting wafer is exposed through a set of masks, each mask of which comprises a region to form a cutting line surrounding the image zone, the row addressing blocks and the column reading blocks; the cutting line facilitating the cutting of the semi-conducting wafer; the method comprising, furthermore, a step of cutting the semi-conducting wafer along the cutting line to form a sensor.

12. The imaging device obtained by a photolithographic method as claimed in claim 1 .

13. The imaging device as claimed in claim 12 , in which at least two column reading blocks are contiguous with pixels belonging to rows of distinct ranks.

14. The imaging device as claimed in claim 12 , in which the number of pixels per column is adapted in such a way that the peripheral pixels of the image zone form substantially a polygon comprising at least 5 sides.

15. The imaging device as claimed in claim 14 , in which the polygon comprises a number less than 20 of sides.

16. The imaging device as claimed in claim 14 , in which the peripheral pixels of the image zone form substantially a regular octagon.

17. The imaging device as claimed in one of claim 14 , in which the column reading blocks are clustered together in groups, each group being parallel to one of the sides of the polygon.

18. The imaging device as claimed in claim 16 , in which the column reading blocks of a first group are situated on a first side of the regular octagon, the column reading blocks of a second group are situated on a second side adjacent to the first, and the column reading blocks of a third group are situated on a third side adjacent to the second side.

19. The imaging device as claimed in claim 12 , in which the row addressing blocks are situated at the periphery of the image zone.

20. The imaging device as claimed in claim 18 , in which the row addressing blocks are situated on sides of the regular octagon that are opposite the first, the second and the third side, the row conductors being formed on a first face of the substrate, comprising, furthermore, control buses formed on a second face (metallic layer) of the substrate and metallized holes formed in the image zone, the control buses being oriented parallel to the columns of pixels and being linked to the row addressing blocks, the metallized holes linking each row conductor (X i , X RAZi ) to one of the control buses.

21. The imaging device as claimed in claim 18 , in which the row addressing blocks are situated on the same sides of the regular octagon as the column reading blocks, the row conductors being formed on a first face (metallic layer) of the substrate, comprising, furthermore, control buses formed on a second face (metallic layer) of the substrate and metallized holes formed in the image zone, the control buses being oriented parallel to the columns of pixels and being linked to the row addressing blocks, the metallized holes linking each row conductor (X i , X RAZi ) to one of the control buses.

22. The imaging device as claimed in claim 16 , in which the column reading blocks are situated on a part of a first side of the regular octagon, on a second side adjacent to the first side, on a part of a third side opposite the first side, and on a fourth side opposite the second side, the parts of the first and third sides being complementary so as to allow the reading of each of the columns of pixels of the image zone, the row addressing blocks being situated on a part of a fifth side adjacent to the second side, on a sixth side adjacent to the third and fifth sides, on a part of a seventh side opposite the fifth side, and on an eighth side opposite the sixth side, the parts of the fifth and seventh sides being complementary so as to allow the addressing of each of the rows of pixels of the image zone.

23. The imaging device as claimed in claim 11 , in whi

Assignees

• Commissariat Energie Atomique
• Trixell

Inventors

• Rohr Pierre
• Martin Jean-Luc
• Bosset Bruno
• Dupont Bertrand

Classifications

• H04N25/74

  Circuitry for scanning or addressing the pixel array · CPC title

• H04N25/767

  Horizontal readout lines, multiplexers or registers · CPC title

• H04N25/702

  SSIS architectures characterised by non-identical, non-equidistant or non-planar pixel layout · CPC title

• H10F77/1237

  having at least three elements, e.g. HgCdTe · CPC title

• H10F77/124

  comprising only Group III-V materials, e.g. GaAs · CPC title