Semiconductor devices

Patent metadata

Field	Value
Publication number	US-9385105-B2
Application number	US-201314370971-A
Country	US
Kind code	B2
Filing date	Jan 10, 2013
Priority date	Jan 10, 2012
Publication date	Jul 5, 2016
Grant date	Jul 5, 2016

Abstract

A semiconductor device includes: a chip having at least one electrically conductive contact at a first side of the chip; an extension layer extending laterally from one or more sides of the chip; a redistribution layer on a surface of the extension layer and the first side, and coupled to the contact; an interposer having at least one electrically conductive contact at a first surface of the interposer and coupled to the redistribution layer, and at least one electrically conductive contact at a second surface of the interposer opposite to the first surface; a molding material at least partially enclosing the chip and the redistribution layer, and in contact with the interposer. Another semiconductor device includes: an interposer; a redistribution layer over the interposer; a circuit having first and second circuit portions, wherein the redistribution layer includes the first circuit portion, and the interposer includes the second circuit portion.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor device, the method comprising:
forming a redistribution layer on a surface of a layer that comprises a first semiconductor chip and an extension layer, wherein the redistribution layer extends beyond a boundary of the first semiconductor chip;
forming a plurality of electrical pads above the redistribution layer configured to connect the semiconductor chip to the redistribution layer,
connecting an interposer to a plurality of electrical connectors on the bottom side of the redistribution layer; and
forming a ball grid array on a surface of the interposer that is opposite the plurality of electrical connectors.

2. The method of claim 1 , wherein the interposer comprises a Printed Circuit Board interposer.

3. The method of claim 1 , wherein a first pitch of electrically conductive contacts of the first semiconductor chip is smaller than a second pitch of the electrical connectors, and wherein the second pitch is smaller than a third pitch of the ball grid array.

4. The method of claim 3 , wherein the plurality of electrical connectors comprises a plurality of copper cylinders.

5. The method of claim 3 , wherein the plurality of electrical connectors comprises a plurality of solder bumps.

6. The method of claim 5 , wherein a first pitch of electrically conductive contacts of the first semiconductor chip is below a 100 micron pitch.

7. The method of claim 1 , further comprising embedding a second semiconductor chip in the interposer.

8. The method of claim 1 , wherein the interposer comprises electrical interconnects configured to carry electrical signals from one or more electrical contacts from an upper surface of the interposer to one or more electrical contacts at a lower surface of the interposer; wherein a quantity of the electrical contacts at the upper surface of the interposer is unequal to a quantity of the electrical contacts at the lower surface of the interposer.

Assignees

• Intel Deutschland Gmbh

Inventors

• Meyer Thorsten
• Ofner Gerald
• Waidhas Bernd
• Barth Hans-Joachim
• Albers Sven
• Golly Reinhard
• Riess Philipp
• Ebersberger Bernd

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W74/121

  by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation · CPC title

• H10W74/019

  using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title