Chip diode and diode package

Patent metadata

Field	Value
Publication number	US-9385093-B2
Application number	US-201514703928-A
Country	US
Kind code	B2
Filing date	May 5, 2015
Priority date	Oct 17, 2011
Publication date	Jul 5, 2016
Grant date	Jul 5, 2016

Abstract

A chip diode includes a plurality of diode cells formed on a semiconductor substrate, each having a diode junction region; and parallel connection portions provided on the substrate to connect the diode cells in parallel and including a first electrode formed in one side of the substrate and having at least two extending portions extending only to another side of the substrate. At least two diode junction regions are formed along each of the extending portions. At least two extending portions are formed to have line symmetry and at least four diode junction regions are formed to have point symmetry and line symmetry in a plane view. A space is formed in the center of at least the four diode junction regions. Fluctuations in characteristics of the diode are suppressed even when a large stress is applied to a pad of a diode package for electrical connection with the exterior.

First claim

What is claimed is:

1. A chip diode, comprising:
a semiconductor substrate;
a plurality of diode cells formed on the semiconductor substrate, each diode cell of the plurality of diode cells having an individual diode junction region; and
parallel connection portions provided on the semiconductor substrate and connecting the plurality of diode cells in parallel, the parallel connection portions including a first electrode formed in one side of the semiconductor substrate and having at least two extending portions extending only to another side of the semiconductor substrate,
wherein at least two diode junction regions are formed along each of the at least two extending portions,
wherein at least two extending portions are formed to have line symmetry and at least four diode junction regions formed along the at least two extending portions are formed to have point symmetry and line symmetry in a plane view, and
wherein each of at least the four diode junction regions has an outline and each outline has a line extending obliquely in a direction in which the extending portion extends in a plane view so that a space is formed in the center of at least the four diode junction regions.

2. The chip diode according to claim 1 , wherein each of the diode junction regions is a p-n junction region.

3. The chip diode according to claim 2 , wherein the semiconductor substrate is constituted of a semiconductor of a first conductivity type and each diode cell has a region of a second conductivity type formed on the semiconductor substrate.

4. The chip diode according to claim 3 , wherein the first electrode is in common contact with the regions of the second conductivity type provided respectively in the plurality of diode cells and the parallel connection portions further include a second electrode electrically connected to the semiconductor substrate.

5. The chip diode according to claim 4 , further including a first conductivity type region formed on the semiconductor substrate and having a higher impurity concentration than the semiconductor substrate, wherein the second electrode is bonded to the first conductivity type region.

6. The chip diode according to claim 4 , wherein the first electrode and the second electrode are formed on one of the surfaces of the semiconductor substrate.

7. The chip diode according to claim 5 , wherein the first electrode and the second electrode are formed on one of the surfaces of the semiconductor substrate.

8. The chip diode according to claim 1 , wherein each of the diode junction regions is a Schottky junction region.

9. The chip diode according to claim 8 , wherein the first electrode has a Schottky metal in contact with the Schottky junction regions of the plurality of diode cells, and the parallel connection portions further include a second electrode electrically connected to the semiconductor substrate.

10. The chip diode according to claim 9 , wherein the first electrode and the second electrode are formed on one of the surfaces of the semiconductor substrate.

11. The chip diode according to claim 1 , wherein the diode junction regions of the plurality of diode cells are formed to be equal in size.

12. The chip diode according to claim 1 , wherein each diode junction region is a polygonal region.

13. The chip diode according to claim 1 , wherein the plurality of diode cells are formed to be equal in size.

14. The chip diode according to claim 1 , wherein the plurality of diode cells are arrayed two-dimensionally at equal intervals.

15. The chip diode according to claim 1 , wherein not less than four of the diode cells are provided.

Assignees

• Rohm Co Ltd

Inventors

• Yamamoto Hiroki

Classifications

• H10W72/5522

  comprising gold [Au] · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W72/877

  Bump connectors and die-attach connectors · CPC title