Semiconductor device with bump structure on an interconncet structure

Patent metadata

Field	Value
Publication number	US-9385076-B2
Application number	US-201113313677-A
Country	US
Kind code	B2
Filing date	Dec 7, 2011
Priority date	Dec 7, 2011
Publication date	Jul 5, 2016
Grant date	Jul 5, 2016

Abstract

A semiconductor device includes a post-passivation interconnect (PPI) structure having a landing pad region. A polymer layer is formed on the PPI structure and patterned with a first opening and a second opening to expose portions of the landing pad region. The second opening is a ring-shaped opening surrounding the first opening. A bump structure is formed on the polymer layer to electrically connect the landing pad region through the first opening and the second opening.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a passivation layer overlying a semiconductor substrate;
an interconnect structure overlying the passivation layer;
a protective layer overlying the interconnect structure and comprising a first opening and a second opening exposing portions of the interconnect structure, wherein the first opening is surrounded by the second opening, and the first opening is separated from the second opening by at least a portion of the protective layer, and the second opening is located closer to an edge of a landing pad region than the first opening;
a barrier layer within the first opening and the second opening; and
a continuous bump structure overlying the protective layer and electrically connected to the interconnect structure through the first opening and the second opening, wherein the continuous bump structure extends into at least one of the first opening or the second opening.

2. The semiconductor device of claim 1 , wherein the second opening is a continuous ring-shaped opening.

3. The semiconductor device of claim 1 , wherein the second opening is a discontinuous ring-shaped opening.

4. The semiconductor device of claim 3 , wherein the second opening comprises at least two separated sub-openings.

5. The semiconductor device of claim 1 , the solder bump extends into both the first opening and the second opening.

6. The semiconductor device of claim 1 , wherein the bump structure comprises a solder bump.

7. The semiconductor device of claim 6 , wherein the solder bump partially fills the first opening and the second opening.

8. The semiconductor device of claim 6 , wherein the barrier layer is between the solder bump and the interconnect structure.

9. The semiconductor device of claim 8 , wherein a top surface of the barrier layer is below a top surface of the protective layer.

10. The semiconductor device of claim 8 , wherein the barrier layer comprises at least one of a nickel (Ni) layer, a palladium (Pd) layer or a gold (Au) layer.

11. The semiconductor device of claim 1 , wherein the protective layer comprises a polymer, and the interconnect structure comprises copper.

12. A semiconductor device, comprising:
an interconnect structure over a substrate;
a protective layer over the interconnect structure and comprising a first opening and a second opening, wherein each of the first opening and the second opening expose portions of the interconnect structure, the first opening is at least partially surrounded by the second opening, the second opening is located closer to an edge of a landing pad region than the first opening, and the first opening is separated from the second opening by at least a portion of the protective layer;
a barrier layer in the first opening and in the second opening, wherein the barrier layer fills less than an entirety of the first opening and the second opening; and
a bump structure over the barrier layer and electrically connected to the interconnect structure, wherein the bump structure comprises a solder bump extending into at least one of the first opening or the second opening.

13. The semiconductor device of claim 12 , wherein a ratio of a height of the second opening to a height of the first opening of the barrier layer ranges from about 1.0 to about 1.5.

14. The semiconductor device of claim 12 , wherein a top surface of the barrier layer is above a top surface of the protective layer.

15. The semiconductor device of claim 12 , wherein the second opening comprises a first sub-opening separated from a second sub-opening by a distance, wherein the distance ranges from about 1 micron μm) and about 30 μm.

16. The semiconductor device of claim 12 , wherein the interconnect structure comprises a landing pad region configured to electrically connect to the bump structure, wherein a distance from an outer edge of the second opening to an outer edge of the landing pad region ranges from about 1 μm to about 10 μm.

17. A semiconductor device, comprising:
an interconnect structure over a substrate, wherein the interconnect structure includes a landing pad region;
a protective layer over the interconnect structure;
a first opening in the protective layer, the first opening exposing the landing pad region;
at least one second opening in the protective layer, each second opening of the at least one second opening exposing the landing pad region, wherein the at least one second opening is located closer to an outer edge of the landing pad region than the first opening, and the first opening is separated from the second opening by at least a portion of the protective layer;
a barrier layer partially filling the first opening and the at least one second opening; and
a bump structure over the barrier layer and electrically connected to the landing pad region, wherein the bump structure comprises a solder bump extending into at least one of the first opening or the second opening.

18. The semiconductor device of claim 17 , wherein the barrier layer in the second opening is thicker than the barrier layer in the first opening.

19. The semiconductor device of claim 17 , wherein the solder bump extends into both of the first opening and the second opening.

20. The semiconductor device of claim 17 , wherein the second opening is a discontinuous ring-shaped opening.

Assignees

• Chen Hsien-Wei
• Wu Yi-Wen
• Lu Wen-Hsiung
• Taiwan Semiconductor Mfg

Inventors

• Chen Hsien-Wei
• Wu Yi-Wen
• Lu Wen-Hsiung

Classifications

• H10W74/147

  the encapsulations being multilayered · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/9223

  with redistribution layers [RDL] · CPC title

• H10W72/983

  Reinforcing structures, e.g. collars · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title