Gate contact structure for FinFET

Patent metadata

Field	Value
Publication number	US-9385069-B2
Application number	US-201313789145-A
Country	US
Kind code	B2
Filing date	Mar 7, 2013
Priority date	Mar 7, 2013
Publication date	Jul 5, 2016
Grant date	Jul 5, 2016

Abstract

An embodiment includes a substrate, wherein a portion of the substrate extends upwards forming a fin, a gate dielectric over a top surface and at least portions of sidewalls of the fin, a gate electrode over the gate dielectric, and a contact over and extending into the gate electrode, wherein the contact has a first width above the gate electrode and a second width within the gate electrode, the first width being smaller than the second width.

First claim

What is claimed is:

1. An integrated circuit structure (IC) comprising:
a substrate, wherein a portion of the substrate extends upwards forming a fin;
a gate dielectric over a top surface and at least portions of sidewalls of the fin;
a gate electrode over the gate dielectric; and
a contact over and extending into the gate electrode, wherein the contact has a first width above the gate electrode and a second width within the gate electrode, the first width being smaller than the second width, wherein a top surface of the gate electrode is higher than a bottom surface of the contact, and wherein a first portion of the contact above the gate electrode and a second portion of the contact within the gate electrode are formed of a same conductive material.

2. The IC structure of claim 1 , wherein a ratio of the second width to a third width of the fin is between about 1.2 and about 2.5.

3. The IC structure of claim 1 , further comprising a contact barrier layer between the contact and the gate electrode, wherein the contact barrier layer further covers sidewalls of the contact.

4. The IC structure of claim 3 , wherein the contact barrier layer comprises titanium nitride or tantalum nitride.

5. The IC structure of claim 3 , wherein the contact barrier layer comprises titanium aluminum nitride, titanium aluminum tungsten nitride, tantalum aluminum nitride, or tantalum aluminum tungsten nitride.

6. The IC structure of claim 1 , wherein the contact comprises tungsten, copper, or aluminum.

7. The IC structure of claim 1 , wherein the gate dielectric comprises silicon oxide, silicon nitride, or a high-k dielectric material.

8. An integrated circuit (IC) structure comprising:
a substrate;
a semiconductor fin over and connected to the substrate;
a gate dielectric over a top surface and sidewalls of the fin;
a gate electrode over the gate dielectric;
an inter-layer dielectric (ILD) over the gate dielectric;
a contact extending from a top surface of the ILD into the gate electrode, wherein the contact has a first portion in the ILD and a second portion in the gate electrode, and wherein the first and second portion have a first and second width respectively, the second width being larger than the first width; and
a continuous contact barrier layer comprising:
a first portion disposed on a bottom surface of the contact and adjoining the gate electrode;
a second portion disposed on an upper lateral surface of the contact and adjoining the ILD, wherein an interface between the second portion and the ILD is aligned with an interface between an upper lateral surface of the gate electrode and the ILD; and
a third portion disposed on sidewalls of the contact and adjoining the ILD.

9. The IC structure of claim 8 , wherein a ratio of the second width to a third width of the fin is between about 1.2 and about 2.5.

10. The IC structure of claim 8 , wherein the contact barrier layer comprises titanium nitride or tantalum nitride.

11. The IC structure of claim 8 , wherein the contact barrier layer comprises titanium aluminum nitride, titanium aluminum tungsten nitride, tantalum aluminum nitride, or tantalum aluminum tungsten nitride.

12. The IC structure of claim 8 further comprising an interfacial layer between the gate dielectric and the fin.

13. The IC structure of claim 8 , further comprising a dielectric layer between the gate dielectric and the fin, wherein the dielectric layer includes a first and a second portion disposed on opposite sides of the fin.

14. The IC structure of claim 8 , wherein the gate electrode comprises a signal metal and a work function metal.

15. An integrated circuit (IC) structure comprising:
a gate comprising a gate electrode;
an inter-layer dielectric (ILD) over the gate;
a gate contact in the ILD and extending into the gate electrode, wherein the gate contact comprises a first width in the ILD and a second width in the gate electrode, wherein the first width is smaller than the second width, and wherein a first portion of the gate contact in the ILD and a second portion of the gate contact in the gate electrode are formed of a same conductive material; and
a contact barrier layer disposed between gate contact and the ILD, wherein a portion wherein a top surface of the contact barrier layer is substantially level with a top surface of the gate electrode.

16. The IC structure of claim 15 , further comprising a substrate comprising a portion extending upwards forming a fin, wherein the gate is disposed over the substrate and extends along sidewalls of the fin.

17. The IC structure of claim 16 , wherein a ratio of the second width to a third width of the fin is between about 1.2 and about 2.5.

18. The IC structure of claim 15 further comprising a gate dielectric disposed under the gate electrode.

19. The IC structure of claim 15 , wherein the contact barrier layer is disposed on sidewalls, a top surface, and a bottom surface of the gate contact.

20. The IC structure of claim 15 , wherein the contact barrier layer comprises titanium nitride, tantalum nitride, titanium aluminum nitride, titanium aluminum tungsten nitride, tantalum aluminum nitride, or tantalum aluminum tungsten nitride.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Liu Chi-Wen
• Wang Chao-Hsiung

Classifications

• H10P50/667

  by liquid etching only · CPC title

• H10P50/267

  using plasmas · CPC title

• H10P50/266

  by vapour etching only · CPC title

• H10P50/264

  by chemical means · CPC title

• H10P50/00

  Etching of wafers, substrates or parts of devices · CPC title