Heat sink having a through-opening

US9385064B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9385064-B2
Application numberUS-201414262894-A
CountryUS
Kind codeB2
Filing dateApr 28, 2014
Priority dateApr 28, 2014
Publication dateJul 5, 2016
Grant dateJul 5, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A semiconductor structure includes a heat sink. The heat sink having a first major surface, a second major surface, a first sidewall surface, and a through-opening extending from one of the first sidewall surface or the first major surface of the heat sink to the second surface of the heat sink, and wherein the through-opening has an inflow region, a restrictive region, and an outflow region. The restrictive region is located between the inflow region and the outflow region, wherein the inflow region has an inflow surface opening at the one of the first sidewall or the first major surface, and the outflow region has an outflow surface opening at the second major surface. A cross-sectional area of the restrictive region is less than an area of the inflow surface opening and less than an area of the outflow surface opening.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor structure, comprising: a heat sink having: a first major surface and a second major surface opposite the first major surface, wherein at least a portion of the first major surface includes a thermal contact area for a semiconductor die, the thermal contact area surrounded by a semiconductor die perimeter; a first sidewall surface between the first and second major surfaces; and a through-opening extending from the first major surface of the heat sink to the second major surface of the heat sink, wherein the through-opening has an inflow region, a restrictive region, and an outflow region, the restrictive region located between the inflow region and the outflow region, wherein the inflow region has an inflow surface opening at the first major surface, and the outflow region has an outflow surface opening at the second major surface, wherein a cross-sectional area of the restrictive region is less than an area of the inflow surface opening and less than an area of the outflow surface opening. 2. The semiconductor structure of claim 1 , wherein the semiconductor die perimeter corresponds to a perimeter which surrounds the semiconductor die after attachment to the semiconductor die. 3. The semiconductor structure of claim 1 , wherein the restrictive region overlaps the semiconductor die perimeter. 4. The semiconductor structure of claim 1 , wherein the restrictive region is located within the semiconductor die perimeter. 5. The semiconductor structure of claim 1 , wherein the inflow region extends from the first major surface to the restrictive region, and the inflow surface opening is located outside the semiconductor die perimeter. 6. The semiconductor structure of claim 1 , wherein the cross-sectional area of the restrictive region is as measured substantially perpendicular from a sidewall of the restrictive region. 7. The semiconductor structure of claim 1 , wherein the sidewall surface is substantially perpendicular to the second major surface. 8. The semiconductor structure of claim 1 , wherein the heat sink further includes a second sidewall surface between the first and second major surfaces, wherein the through-opening further includes a second inflow region extending from one of the second sidewall surface or the first sidewall surface to the restrictive region of the through-opening, wherein the second inflow region has a second inflow surface opening at the one of the second sidewall surface or the first sidewall surface, wherein the cross-sectional area of the restrictive region is less than an area of the second inflow surface opening. 9. The semiconductor structure of claim 1 , wherein the heat sink further includes: a second sidewall between the first and second major surfaces; and a second through-opening extending from one of the second sidewall surface or the first major surface of the heat sink to the second major surface of the heat sink, wherein the second through-opening has an inflow region, a restrictive region, and an outflow region, wherein the inflow region has an inflow surface opening at the one of the second sidewall or the first major surface, and the outflow region has an outflow surface opening at the second major surface, wherein a cross-sectional area of the restrictive region is less than an area of the inflow surface opening of the second through-opening and less than an area of the outflow surface opening of the second through-opening. 10. The semiconductor structure of claim 9 , wherein each of the through-opening and the second through-opening overlap the semiconductor die perimeter. 11. The semiconductor structure of claim 1 , wherein the inflow region extends from the first major surface to the restrictive region, and the restrictive region is located above the inflow surface opening with respect to the first major surface of the heat sink. 12. The semiconductor structure of claim 1 , further comprising: the semiconductor die, wherein the first major surface of the heat sink is attached to the semiconductor die within the thermal contact area with a thermal interface material. 13. A semiconductor structure, comprising: a heat sink having: a first major surface and a second major surface opposite the first major surface, wherein at least a portion of the first major surface includes a thermal contact area for a semiconductor die, the thermal contact area surrounded by a semiconductor die perimeter; a first sidewall surface between the first and second major surfaces; and a through-opening extending from each of the first major surface and the first sidewall surface, through the heat sink, to the second major surface, and having a first inflow region, a second inflow region, a restrictive region, and an outflow region, wherein the outflow region extends from the restrictive region to the second major surface and has an outflow surface opening at the second major surface, the first inflow region extends from the first sidewall surface to the restrictive region and has a first inflow surface opening at the first sidewall surface, and the second inflow region extends from the first major surface to the restrictive region and has a second inflow surface opening at the first major surface, wherein a cross-sectional area of the restrictive region is less than an area of the first inflow surface opening, less than an area of the second inflow surface opening, and less than an area of the outflow surface opening. 14. The semiconductor structure of claim 13 , wherein the restrictive region is located above the second inflow surface opening with respect to the first major surface. 15. The semiconductor structure of claim 13 , wherein the semiconductor die perimeter corresponds to a perimeter which surrounds the semiconductor die after attachment to the semiconductor die. 16. The semiconductor structure of claim 13 , wherein the restrictive region overlaps the semiconductor die perimeter. 17. The semiconductor structure of claim 13 , wherein the restrictive region is located within the semiconductor die perimeter. 18. The semiconductor structure of claim 13 , wherein each of the first inflow region and the second inflow region is located outside the semiconductor die perimeter. 19. The semiconductor structure of claim 13 , further comprising: the semiconductor die, wherein the first major surface of the heat sink is attached to the semiconductor die within the thermal contact area with a thermal interface material. 20. A semiconductor structure, comprising: a heat sink having: a first major surface and a second major surface opposite the first major surface; a first sidewall surface between the first and second major surfaces; and a through-opening extending from the first major surface of the heat sink to the second major surface of the heat sink, wherein the through-opening has an inflow region, a restrictive region, and an outflow region, the restrictive region located between the inflow region and the outflow region, wherein the inflow region has an inflow surface opening at the first major surface, and the outflow region has an outflow surface opening at the second major surface, wherein a cross-sectional area of the restrictive region is less than an area of the inflow surface opening and less than an area of the outflow surface opening; and a semiconductor die, wherein the first major surface of the heat sink is attached to the semiconductor die with a thermal interface material, and wherein the restrictive region overlaps a per

Assignees

Inventors

Classifications

  • Bump connectors and die-attach connectors · CPC title

  • not comprising solid metals or solid metalloids, e.g. ceramics · CPC title

  • comprising polymers · CPC title

  • Die-attach connectors having a filler embedded in a matrix · CPC title

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

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What does patent US9385064B2 cover?
A semiconductor structure includes a heat sink. The heat sink having a first major surface, a second major surface, a first sidewall surface, and a through-opening extending from one of the first sidewall surface or the first major surface of the heat sink to the second surface of the heat sink, and wherein the through-opening has an inflow region, a restrictive region, and an outflow region. T…
Who is the assignee on this patent?
Uehling Trent S, Freescale Semiconductor Inc
What technology area does this patent fall under?
Primary CPC classification H10W40/43. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 05 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).