Method for providing a self-aligned pad protection in a semiconductor device

Patent metadata

Field	Value
Publication number	US-9385031-B2
Application number	US-201514830766-A
Country	US
Kind code	B2
Filing date	Aug 20, 2015
Priority date	Dec 23, 2013
Publication date	Jul 5, 2016
Grant date	Jul 5, 2016

Abstract

According to one embodiment, a method for processing a semiconductor device is provided including forming a final metal layer forming a passivation layer over the final metal layer and structuring the passivation layer and the final metal layer to form a patterned metal layer and a patterned passivation layer, wherein the patterned metal layer includes a pad region covered by the patterned passivation layer.

First claim

What is claimed is:

1. A method for processing a semiconductor device, comprising:
forming a final metal layer;
depositing a first passivation layer in not fully cured state over the final metal layer;
structuring the first passivation layer, while it is in not fully cured state, to open a portion of the final metal layer;
depositing, while the first passivation layer is in not fully cured state, a second passivation layer over the first passivation layer and over the portion of the final metal layer; and
after depositing the second passivation layer, at least partially curing the first passivation layer.

2. The method according to claim 1 , wherein during curing of the first passivation layer the first passivation layer shrinks and portions of the second passivation layer deposited on the first passivation layer detach from the first passivation layer or sink into the first passivation layer.

3. The method according to claim 1 , wherein the first passivation layer includes an organic precursor.

4. The method according to claim 1 , wherein the first passivation layer includes an imide.

5. The method according to claim 1 , wherein the first passivation layer includes a photosensitive polyimide.

6. The method according to claim 1 , wherein at least partially curing the first passivation layer includes curing the first passivation to a state that is more fully cured than the not fully cured state.

7. The method according to claim 1 , wherein at least partially curing the first passivation layer includes hard baking the first passivation layer.

8. The method according to claim 1 , wherein at least partially curing the first passivation includes polymerizing the first passivation layer.

9. The method according to claim 1 , wherein the second passivation layer comprises a metal oxide.

10. The method according to claim 1 , wherein the second passivation layer is deposited by means of an atomic layer deposition process.

11. The method according to claim 1 , wherein the second passivation layer is formed over the whole surface of the first passivation layer and the portion of the metal layer.

12. A method for processing a semiconductor device, comprising:
forming a final metal layer;
depositing a first passivation layer over the final metal layer;
partially polymerizing the first passivation layer;
structuring the first passivation layer, while it is in partially polymerized state, to open a portion of the final metal layer;
depositing, while the first passivation layer is in partially polymerized state, a second passivation layer over the first passivation layer and over the portion of the final metal layer; and
after depositing the second passivation layer, polymerizing the first passivation layer.

Assignees

• Infineon Technologies Ag

Inventors

• Rogalli Michael
• Lehnert Wolfgang

Classifications

• H10P95/08

  Planarisation of organic insulating materials · CPC title

• H10P76/202

  for lift-off processes · CPC title

• H10P50/667

  by liquid etching only · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title