Method of manufacturing wiring substrate

Patent metadata

Field	Value
Publication number	US-9380707-B2
Application number	US-201314090076-A
Country	US
Kind code	B2
Filing date	Nov 26, 2013
Priority date	Dec 4, 2012
Publication date	Jun 28, 2016
Grant date	Jun 28, 2016

Abstract

A method of manufacturing a wiring substrate includes: preparing a laminated plate of a metal layer and an insulating layer; adhering the laminated plate to a first support body facing the metal layer; and forming a first wiring layer with vias extending through the insulating layer and first pads exposed from a first surface of the insulating layer. The method also includes: separating a multilayer structure including the metal, insulating, and first wiring layer from the first support body; adhering the multilayer structure to a second support body facing the first wiring layer; removing the metal layer; forming a plurality of second wiring layers including second pads connected to the vias and exposed from a second surface of the insulating layer opposite the first surface; and separating the insulating, the first wiring, and the plurality of second wiring layers from the second support body, to obtain the wiring substrate.

First claim

The invention claimed is:

1. A method of manufacturing a wiring substrate, the method comprising:
preparing a laminated plate in which a metal layer and an insulating layer are laminated;
adhering the laminated plate to a first support body with the metal layer facing the first support body;
forming a first wiring layer including vias that extend through the insulating layer and first pads exposed from a first surface of the insulating layer;
separating from the first support body a multilayer structure including the metal layer, the insulating layer, and the first wiring layer;
adhering the multilayer structure to a second support body with the first wiring layer facing the second support body;
removing the metal layer with the second support body supporting the first wiring layer and the insulating layer;
forming a plurality of second wiring layers including second pads that are connected to the vias and exposed from a second surface of the insulating layer that is opposite to the first surface; and
separating the insulating layer, the first wiring layer, and the plurality of second wiring layers from the second support body to obtain the wiring substrate.

2. The method according to claim 1 , wherein the first wiring layer and the plurality of second wiring layers are formed through a semi-additive process.

3. The method according to claim 1 , wherein the insulating layer is an organic resin layer.

4. The method according to claim 1 , wherein the insulating layer includes a plurality of insulating layers.

5. The method according to claim 1 , wherein the forming a first wiring layer includes forming the vias and the first pads in the insulating layer with the first support body supporting the laminated plate.

6. The method according to claim 1 , wherein the metal layer is removed with the second support body supporting the multilayer structure.

7. The method according to claim 1 , wherein the plurality of second wiring layers are formed with the second support body supporting the multilayer structure.

8. A method of manufacturing a wiring substrate, the method comprising:
preparing a laminated plate in which a metal layer and an insulating layer are laminated;
adhering the laminated plate to a first support body with the metal layer facing the first support body;
forming a first wiring layer including vias that extend through the insulating layer and first pads exposed from a first surface of the insulating layer;
separating from the first support body a multilayer structure including the metal layer, the insulating layer, and the first wiring layer;
adhering the multilayer structure to a second support body with the first wiring layer facing the second support body;
removing the metal layer;
forming a plurality of second wiring layers including second pads that are connected to the vias and exposed from a second surface of the insulating layer that is opposite to the first surface; and
separating the insulating layer, the first wiring layer, and the plurality of second wiring layers from the second support body to obtain the wiring substrate,
wherein the adhering the laminated plate to the first support body includes
forming a first adhesive layer on an edge of one surface of the first support body facing the metal layer, and
adhering the laminated plate to the first support body through the first adhesive layer.

9. A method of manufacturing a wiring substrate, the method comprising:
preparing a laminated plate in which a metal layer and an insulating layer are laminated;
adhering the laminated plate to a first support body with the metal layer facing the first support body;
forming a first wiring layer including vias that extend through the insulating layer and first pads exposed from a first surface of the insulating layer;
separating from the first support body a multilayer structure including the metal layer, the insulating layer, and the first wiring layer;
adhering the multilayer structure to a second support body with the first wiring layer facing the second support body;
removing the metal layer;
forming a plurality of second wiring layers including second pads that are connected to the vias and exposed from a second surface of the insulating layer that is opposite to the first surface; and
separating the insulating layer, the first wiring layer, and the plurality of second wiring layers from the second support body to obtain the wiring substrate, wherein the adhering the multilayer structure to the second support body includes
forming a second adhesive layer at an edge of one surface of the second support body facing the first wiring layer, and
adhering the multilayer structure to the second support body through the second adhesive layer.

Assignees

• Shinko Electric Ind Co

Inventors

• Shimizu Noriyoshi
• Rokugawa Akio
• Koyama Toshinori
• Kaneda Wataru

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/095

  of vias therein · CPC title