Integrated circuit and semiconductor device including the same

Patent metadata

Field	Value
Publication number	US-9379705-B2
Application number	US-201514624646-A
Country	US
Kind code	B2
Filing date	Feb 18, 2015
Priority date	Feb 21, 2014
Publication date	Jun 28, 2016
Grant date	Jun 28, 2016

Abstract

An integrated circuit (IC) includes at least one unit cell. The at least one unit cell includes a first bit circuit configured to process a first bit signal, a second bit circuit configured to process a second bit signal, a first well spaced apart from boundaries of the at least one unit cell and biased to a first voltage, and a second well biased to a second voltage that is different from the first voltage. Each of the first and second bit circuits includes at least one transistor from among a plurality of transistors disposed in the first well.

First claim

What is claimed is:

1. An integrated circuit (IC) comprising at least one unit cell, wherein the at least one unit cell comprises:
a first bit circuit configured to process a first bit signal;
a second bit circuit configured to process a second bit signal;
a first well spaced apart from boundaries of the at least one unit cell and biased to a first voltage;
a second well biased to a second voltage that is different from the first voltage; and
a common circuit configured to receive a control signal and control the first and second bit circuits according to the control signal,
wherein each of the first and second bit circuits comprises at least one transistor from among a plurality of transistors disposed in the first well.

2. The IC of claim 1 , wherein the first and second bit circuits have a same configuration.

3. The IC of claim 1 , wherein a layout of the first bit circuit and a layout of the second bit circuit are symmetrical to each other about an axis that crosses the at least one unit cell.

4. The IC of claim 1 , wherein a layout of the first bit circuit corresponds to a layout of the second bit circuit rotated about a point in the at least one unit cell.

5. The IC of claim 1 , wherein each of the first and second bit circuits comprises a level shifter.

6. The IC of claim 1 , wherein the at least one unit cell further comprises:
a third well biased to the second voltage, wherein the second and third wells each contact one side from a pair of sides of the at least one unit cell that face each other, and the pair of sides corresponds to the boundaries of the at least one unit cell.

7. The IC of claim 6 , wherein the first well is spaced apart from the second and third wells by at least a minimum distance defined by a well-to-well space rule.

8. The IC of claim 6 , wherein the first bit circuit comprises at least one transistor disposed in the second well, and the second bit circuit comprises at least one transistor disposed in the third well.

9. The IC of claim 6 , wherein a length of the at least one unit cell in a first direction is equal to an integer number multiplied by a length of a standard cell in the first direction based on a semiconductor manufacturing process of the IC, and the pair of sides are parallel to the first direction.

10. The IC of claim 6 , wherein an area of the second well and an area of the third well are determined based on a well proximity effect that occurs in adjacent unit cells contacting the pair of sides.

11. The IC of claim 6 , wherein the at least one unit cell further comprises:
a third bit circuit configured to process a third bit signal; and
a fourth bit circuit configured to process a fourth bit signal,
wherein each of the third and fourth bit circuits comprises at least one transistor from among the plurality of transistors disposed in the first well.

12. The IC of claim 11 , wherein the third bit circuit further comprises at least one transistor disposed in the second well, and the fourth bit circuit comprises at least one transistor disposed in the third well.

13. The IC of claim 11 , wherein layouts of the first through fourth bit circuits are respectively disposed in four quadrants of the at least one unit cell.

14. The IC of claim 1 , wherein the common circuit comprises:
a transistor configured to cut off, according to the control signal, a current that flows due to the first voltage or the second voltage to a ground voltage through at least one transistor disposed in each of the first and second bit circuits.

15. The IC of claim 1 , wherein the at least one unit cell comprises:
a first sub-cell and a second sub-cell, each comprising a plurality of bit circuits,
wherein the plurality of bit circuits includes the first and second bit circuits, and each of the first and second sub-cells comprises at least one transistor from among the plurality of transistors disposed in the first well.

16. The IC of claim 15 , wherein the at least one unit cell comprises:
a third sub-cell and a fourth sub-cell,
wherein the third and fourth sub-cells have a same configuration as the first and second sub-cells, and each of the third and fourth sub-cells comprises at least one transistor from among the plurality of transistors disposed in the first well.

17. The IC of claim 16 , wherein layouts of the first through fourth sub-cells are respectively disposed in four quadrants of the at least one unit cell.

18. A method of generating a layout of an integrated circuit (IC), comprising:
receiving a netlist of the IC, wherein the netlist comprises a plurality of bit circuits, and each bit circuit is configured to process a single-bit signal and corresponds to a first unit cell; and
disposing a second unit cell corresponding to two or more bit circuits in the layout of the IC,
wherein the plurality of bit circuits included in the IC are configured to simultaneously process a plurality of single-bit signals included in a multi-bit signal,
wherein the plurality of bit circuits included in the IC are controlled by a common circuit electrically connected to the plurality of bit circuits according to a control signal received by the common circuit.

19. The method of claim 18 , wherein the second unit cell comprises a first well spaced apart from boundaries of the second unit cell and biased to a first voltage, and a second well biased to a second voltage that is different from the first voltage,
wherein each of the two or more bit circuits comprises at least one transistor from among a plurality of transistors disposed in the first well.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Dal-Hee
• Seo Jae-Woo
• Park Min-Ho

Classifications

• H03K19/018507

  Interface arrangements · CPC title

• H03K19/0944

  using MOSFET {or insulated gate field-effect transistors, i.e. IGFET}(H03K19/096 takes precedence) · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• H03K19/018521

  of complementary type, e.g. CMOS · CPC title

• H03K19/0013 Primary

  in field effect transistor circuits · CPC title