Method for mounting a chip and chip package

Patent metadata

Field	Value
Publication number	US-9378986-B2
Application number	US-201414511353-A
Country	US
Kind code	B2
Filing date	Oct 10, 2014
Priority date	Oct 10, 2013
Publication date	Jun 28, 2016
Grant date	Jun 28, 2016

Abstract

Provided is a method of mounting a chip. The method includes: forming a bump at one surface of a cavity formed concavely in an inner direction of a substrate; performing a coining process to flatten a surface of the bump; coating a solder material on the bump subjected to the coining process; and bonding a chip and the bump by melting the solder material, wherein an electrode portion or a metal portion is formed on a bottom of the chip. For a metal substrate according to the present invention, wherein a vertical insulating layer is included, since the electrode portion of the chip and the electrode portion of the substrate have to be electrically connected, the metal substrate is bonded to the electrode portion of the chip using the bump additionally formed on the metal substrate, so the heat generated in the chip can be rapidly transferred to the substrate, and the junction temperature of the chip can be decreased, thereby enhancing the light efficiency and the. In addition, cracking due to the difference of thermal expansion coefficient between solder materials can be prevented by sealing the bonding portion of the chip using the solder materials. Further, since oxidation of the bonding portion is prevented by blocking the contact with the outside, the chip packaging process can be performed without an additional process of filling an inert gas into the internal space wherein the chip is mounted.

First claim

What is claimed is:

1. A chip package, comprising:
a substrate having a plating layer formed on a surface thereof and including a cavity formed concavely in an inner direction;
a chip wherein an electrode portion or a metal portion is formed on a bottom of the chip;
an insulating portion configured to electrically isolate a first conductive portion of the substrate from a second conductive portion of the substrate and wherein the plating layer includes one plated surface of the cavity on the first conductive portion of the substrate and another plated surface of the cavity on the second conductive portion of the substrate electrically isolated from the one plated surface;
a bump formed on the one plated surface of the cavity; and
a solder for bonding the chip and the bump by being melted, and sealing a space between the chip and the substrate formed by bonding the chip and the bump,
and a wire configured to electrically connect the chip and the another plated surface of the cavity on the second conductive portion of the substrate.

2. The chip package according to claim 1 , wherein the chip package comprises a plurality of bumps formed with intervals determined based on heat dissipation characteristics of the bump.

3. The chip package according to claim 1 , further comprising a sealing member for sealing the chip disposed in the cavity.

Assignees

• Point Engineering Co Ltd
• Point Engineering Co Inc

Inventors

• Ahn Bum Mo
• Nam Ki Myung
• Park Seung Ho

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/07352

  changes in structures or sizes · CPC title

• H10W72/07336

  Soldering or alloying · CPC title

• H10W72/07327

  involving guiding structures, e.g. spacers or supporting members · CPC title

• H10W72/01251

  Changing the shapes of bumps · CPC title