Self-aligned contact and method of forming the same

Patent metadata

Field	Value
Publication number	US-9378963-B2
Application number	US-201414159582-A
Country	US
Kind code	B2
Filing date	Jan 21, 2014
Priority date	Jan 21, 2014
Publication date	Jun 28, 2016
Grant date	Jun 28, 2016

Abstract

Some embodiments of the present disclosure relate to a method to form a source/drain SAC for a transistor. The method comprises forming a pair of gate structures within a first dielectric material on a surface of a substrate, which are isolated from the first dielectric material by an etch stop material. A cap material is formed over the pair of gate structures and the first dielectric material. A pattern of mask material is formed by implanting regions of the cap material with dopants. The implanted regions of the cap material are then removed by a selective etch, which forms the pattern of mask material over each gate structure. The pattern of mask material is configured to shield each gate structure during a subsequent etch step to prevent shorting of the gate structure to the SAC.

First claim

What is claimed is:

1. A method of forming a source/drain contact, comprising:
forming a pair of gate structures within a first dielectric material on a surface of a substrate;
forming a cap material over the pair of gate structures and the first dielectric material;
forming a mask material over each gate structure by implanting upper regions of the cap material with dopants while lower regions of the cap material are left un-doped or are left doped at a lower dopant concentration than the upper regions of the cap material, and removing the upper regions of the cap material to expose an upper surface of the first dielectric material while the lower regions of the cap material are left in place to establish the mask material; and
removing the first dielectric material in regions not covered by the mask material.

2. The method of claim 1 , wherein the cap material comprises silicon.

3. The method of claim 1 , wherein the forming of the mask material comprises:
forming an etch stop material over the pair of gate structures;
forming the first dielectric material over the etch stop material at a position between the pair of gate structures;
forming a planar surface comprising the etch stop material over each gate structure and the first dielectric material;
forming a non-planar surface by performing a first selective etch of the planar surface with a first selective etchant that removes the etch stop material over each gate structure; and
forming the cap material over the non-planar surface comprising a recessed area over each gate structure resulting from a topology of the non-planar surface.

4. The method of claim 3 , further comprising:
disposing a photoresist material within recessed area over each gate structure;
performing an implant of first regions of the cap material with dopants while blocking the dopants from reaching second regions of the cap material; and
performing a second selective etch on the cap material with a second selective etchant that removes the first regions and forms a pattern of the mask material from the second regions.

5. The method of claim 4 , wherein the second selective etchant comprises ammonia, water, or a combination thereof.

6. The method of claim 4 , wherein the second selective etchant comprises chlorine, nitrogen trifluoride, or a combination thereof.

7. The method of claim 4 , further comprising:
forming the cap material by disposing an amorphous material over the pair of gate structures and first dielectric material and annealing the amorphous material to form a crystalline material; and
implanting the crystalline material with the dopants to create an etch selectivity between the first and second regions.

8. The method of claim 7 , wherein the implant causes the first regions to transition to an amorphous phase while leaving the second regions in a crystalline phase, resulting in an etch selectivity between the amorphous and crystalline regions.

9. The method of claim 1 , wherein the removing of the first dielectric material further comprises:
etching the first dielectric material between the pair of gate structures to create a recess that exposes the surface of the substrate, while using the mask material to block etching of the pair of gate structures; and
forming the source/drain contact which is electrically connected to the surface of the substrate by filling the recess with a conductive material.

10. The method of claim 9 , where the etching of the first dielectric material comprises:
forming a second dielectric material over the first dielectric material and second regions of cap material;
forming a photoresist pattern comprising an opening in a photoresist material between the pair of gate structures; and
etching through the opening in the photoresist pattern while using the photoresist pattern and the mask material to block etching of the pair of gate structures.

11. The method of claim 1 , wherein the dopants comprise arsenic, boron, germanium, oxygen, phosphorous, or a combination thereof.

12. A method of forming a source/drain contact, comprising:
forming an etch stop material over a pair of gate structures;
forming a first dielectric material over the etch stop material at a position between the pair of gate structures;
forming a planar surface comprising the etch stop material over each gate structure and the first dielectric material;
performing a first selective etch of the planar surface with a first selective etchant that removes the etch stop material over each gate structure resulting in a non-planar surface; and
forming a cap material over the non-planar surface comprising a recessed area over each gate structure resulting from a topology of the non-planar surface.

13. The method of claim 12 , further comprising:
forming a photoresist material within the recessed area over each gate structure;
performing an implant of first regions of the cap material with dopants while blocking the dopants from reaching second regions of the cap material; and
performing a second selective etch on the cap material with a second selective etchant that removes the first regions and forms a pattern of mask material from the second regions.

14. The method of claim 13 , further comprising:
forming the cap material by disposing an amorphous material over the pair of gate structures and first dielectric material and annealing the amorphous material to form a crystalline material; and
performing an implant of the crystalline material with the dopants to create an etch selectivity between the first and second regions;
wherein the implant causes the first regions to transition to an amorphous phase while leaving the second regions in a crystalline phase, resulting in an etch selectivity between the amorphous and crystalline regions.

15. The method of claim 14 , wherein the removing of the first dielectric material further comprises:
forming a second dielectric material over the first dielectric material and second regions of cap material;
forming a photoresist pattern comprising an opening in a photoresist material between the pair of gate structures; and
etching through the opening in the photoresist pattern to etch away the first dielectric material while using the photoresist pattern and the mask material to block etching of the pair of gate structures.

16. A method, comprising:
forming a pair of gate structures on a surface of a semiconductor substrate;
forming a first dielectric material between neighboring sidewalls of the pair of gate structures;
forming a cap layer including sunken cap regions over the pair of gate structures and a raised cap region over the first dielectric material, wherein an upper surface of the raised cap region is higher than upper surfaces of the sunken cap regions;
implanting the raised cap region with dopants and leaving the sunken cap regions un-doped or doped at a lower doping concentration than the raised cap region, and selectively removing the implanted raised cap region to expose an upper surface of the first dielectric material while leaving the sunken cap regions over the pair of gate structures;
removing the first dielectric material to form a recess that exposes the surface of the semiconductor substrate between the pair of gate structures; and
filling the recess with conductive material to form a source/drain contact which is electrically connected to the surface of the semiconductor substrate between the pair of gate structures.

17. The method of claim 16 , further comprising:
prior to forming the first dielectric material, forming a conform

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yeh Cheng-Hao

Classifications

• H10P50/667

  by liquid etching only · CPC title

• H10P50/266

  by vapour etching only · CPC title

• H10P32/302

  Doping polycrystalline silicon or amorphous silicon layers · CPC title

• H10P30/208

  of electrically inactive species · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title