Cell placement optimization
US-2024371942-A1 · Nov 7, 2024 · US
Semiconductor device and method for manufacturing local interconnect structure thereof
US8987136B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8987136-B2 |
| Application number | US-201113380061-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 27, 2011 |
| Priority date | Aug 20, 2010 |
| Publication date | Mar 24, 2015 |
| Grant date | Mar 24, 2015 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
A semiconductor device and a method for manufacturing a local interconnect structure for a semiconductor device is provided. The method includes forming removable sacrificial sidewall spacers between sidewall spacers and outer sidewall spacers on two sides of a gate on a semiconductor substrate, and forming contact through-holes at source/drain regions in the local interconnect structure between the sidewall spacer and the outer sidewall spacer on the same side of the gate immediately after removing the sacrificial sidewall spacers. Once the source/drain through-holes are filled with a conductive material to form contact vias, the height of the contact vias shall be same as the height of the gate. The contact through-holes, which establish the electrical connection between a subsequent first layer of metal wiring and the source/drain regions or the gate region at a lower level in the local interconnect structure, shall be made in the same depth.
First claim
Opening claim text (preview).
What is claimed is: 1. A method for manufacturing a local interconnect structure for a semiconductor device, comprising: providing a semiconductor substrate with a gate, wherein the gate is sealed by a cap layer and sidewall spacers; forming sacrificial sidewall spacers outside the sidewall spacers; forming outer sidewall spacers at outer sides of the sacrificial sidewall spacers, wherein the material of the sacrificial sidewall spacers is different from the materials of the s…
Assignees
Inventors
Classifications
Patent family
Related publications grouped by family.
External sources
Next steps
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US8987136B2 cover?
- A semiconductor device and a method for manufacturing a local interconnect structure for a semiconductor device is provided. The method includes forming removable sacrificial sidewall spacers between sidewall spacers and outer sidewall spacers on two sides of a gate on a semiconductor substrate, and forming contact through-holes at source/drain regions in the local interconnect structure betwee…
- Who is the assignee on this patent?
- Zhong Huicai, Liang Qingqing, Inst Of Microelectronics Cas
- What technology area does this patent fall under?
- Primary CPC classification H10D30/60. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 24 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).