Electron beam lithography methods including time division multiplex loading

Patent metadata

Field	Value
Publication number	US-9378926-B2
Application number	US-201514604488-A
Country	US
Kind code	B2
Filing date	Jan 23, 2015
Priority date	Mar 14, 2013
Publication date	Jun 28, 2016
Grant date	Jun 28, 2016

Abstract

An embodiment of a method of lithography includes generating a beam of electrons. A first pixel and a second pixel are each configured to pattern the beam. Using time domain multiplex loading, the first and second pixels are controlled such that the beam is patterned. The patterning includes receiving a first clock signal and using the first clock signal to generate a second clock signal and a third clock signal. The second clock signal is sent to the first pixel and sending the third clock signal is sent to the second pixel.

First claim

What is claimed is:

1. A method of lithography, comprising:
generating a beam of electrons;
providing a first pixel and a second pixel each configured to pattern the beam;
using time domain multiplex loading to control the first and second pixels in patterning the beam, wherein the use of time domain multiplex loading includes:
receiving a first clock signal;
using the first clock signal to generate a second clock signal and a third clock signal; and
sending the second clock signal to the first pixel and sending the third clock signal to the second pixel.

2. The method of lithography of claim 1 , wherein the using the first clock signal to generate the second and third clock signals is performed by a demultiplexer.

3. The method of lithography of claim 1 , further comprising:
providing data to the first pixel.

4. The method of lithography of claim 3 , wherein the providing the data to the first pixel is performed by placing data on a data path coupled to the first pixel and the second pixel.

5. The method of claim 4 , further comprising:
using a multiplexer to place the data for the first pixel on the data path; and
using the multiplexer to place another data for the second pixel on the data path.

6. The method of claim 1 , wherein each pixel of an array of pixels including the first and second pixel receive a single clock signal.

7. A method of e-beam lithography, comprising:
using an electron source to produce a beam;
patterning the beam using an array of pixels, wherein the patterning includes:
providing a first clock signal to a demultiplexer (demux);
using the demux to generate a plurality of clock signals; and
providing each of the plurality of clock signals to a respective one pixel of the array of pixels.

8. The method of claim 7 , wherein the patterning further comprises:
providing data to a first group of pixels of the array of pixels using a first shared data path; and
providing data to a second group of pixels of the array of pixels using a second shared data path.

9. The method of claim 8 , wherein the patterning further comprises:
providing a single clock signal of the plurality of clock signals to each of the pixels of the first group of pixels.

10. The method of claim 7 , wherein the patterning the beam includes:
providing a first pixel of the array of pixels;
sending data to the first pixel on a data path;
wherein the first pixel uses the provided clock signal to receive the sent data.

11. The method of claim 10 , wherein the first pixel uses at least one of a register and a latch to receive the sent data.

12. The method of claim 7 , wherein the patterning the beam further comprises:
receiving a first data associated with a right direction scan of an associated lithography system;
receiving a second data associated with a left direction scan of the associated lithography system;
selecting one of the first and the second data; and
delivering the selected one of the first and the second data to a pixel of the array of pixels.

13. The method of claim 12 , further comprising:
receiving a third data associated with one of an up direction, a down direction, and a diagonal direction scan of the system; and
delivering the third data to a pixel of the array of pixels.

14. A method of lithography, comprising:
receiving a first data defining a reflectivity status of a first pixel and a second data defining a reflectivity status of a second pixel of an array of electron mirror pixels;
providing the first data aligned with a first clock signal to the first pixel using a data line; and
providing the second data aligned with a second clock signal to the second pixel using the data line.

15. The method of lithography of claim 14 , further comprising:
receiving a third clock signal; and
using a demultiplexer to generate the first and second clock signals from the third clock signal.

16. The method of claim 14 , further comprising:
receiving a third data defining a reflectivity status of the first pixel, wherein the third data is associated with a scan in a first direction and the first data is associated with a scan in a second direction;
determining an actual scan direction of the second direction; and
selecting the first data using a control circuit prior to sending the first data to the first pixel.

17. The method of claim 14 , further comprising:
receiving a third data defining a reflectivity status of a third pixel and a fourth data defining a reflectivity status of a fourth pixel of the array of electron mirror pixels;
providing the third data aligned with the first clock signal to the third pixel using a second data line; and
providing the fourth data aligned with the second clock signal to the fourth pixel using the second data line.

18. The method of claim 14 , wherein the first pixel receives the single data path and the first clock signal, and stores the first data.

19. The method of claim 14 , further comprising:
receiving a plurality of data including the first data and the second data, wherein the plurality of data is associated with a plurality of scan directions; and
determining the first data is for the first pixel and the second data is for the second pixel, wherein the determining is performed by control circuitry prior to sending the first data to the first pixel.

20. The method of claim 14 , further comprising:
generating the first clock signal and the second clock signal from a single clock signal.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Kuo Ming-Zhang
• Yang Ping-Lin
• Lin Cheng-Chung
• Takahashi Osamu
• Dhong Sang Hoo

Classifications

• H01J2237/2485

  Electric or electronic means · CPC title

• H01J2237/31762

  Computer and memory organisation · CPC title

• H01J37/3023 Primary

  Program control · CPC title

• H01J37/3175 Primary

  Projection methods, i.e. transfer substantially complete pattern to substrate · CPC title

• H01J37/3177

  Multi-beam, e.g. fly's eye, comb probe · CPC title