Apparatuses and operation methods associated with resistive memory cell arrays with separate select lines

Patent metadata

Field	Value
Publication number	US-9378818-B2
Application number	US-201414185095-A
Country	US
Kind code	B2
Filing date	Feb 20, 2014
Priority date	Nov 10, 2011
Publication date	Jun 28, 2016
Grant date	Jun 28, 2016

Abstract

The present disclosure includes methods and apparatuses that include resistive memory. A number of embodiments include a first memory cell coupled to a data line and including a first resistive storage element and a first access device, a second memory cell coupled to the data line and including a second resistive storage element and a second access device, an isolation device formed between the first access device and the second access device, a first select line coupled to the first resistive storage element, and a second select line coupled to the second resistive storage element, wherein the second select line is separate from the first select line.

First claim

What is claimed is:

1. A method of operating an array of resistive memory cells, comprising:
applying a first signal to a selected data line coupled to a first memory cell and a second memory cell, wherein the first memory cell includes a first resistive storage element and a first access device, and wherein the second memory cell includes a second resistive storage element and a second access device; and
applying a second signal to a conductive line coupled to an isolation device formed between the first access device and the second access device;
applying a third signal to a first select line coupled to the first resistive storage element;
applying a fourth signal to a second select line coupled to the second resistive storage element;
applying a fifth signal to a selected conductive line coupled to the first access device;
applying a sixth signal to a conductive line coupled to the second access device; and
applying a seventh signal to unselected data lines of the array.

2. The method of claim 1 , wherein applying the fifth signal includes applying a supply voltage; applying the third signal and the seventh signal includes applying a read voltage; and applying the first signal, the second signal, the fourth signal, and the sixth signal includes applying a ground voltage.

3. The method of claim 1 , wherein applying the fifth signal includes applying a supply voltage; applying the first signal includes applying a read voltage; and applying the second signal, the third signal, the fourth signal, the sixth signal, and the seventh signal includes applying a ground voltage.

4. The method of claim 1 , wherein applying the fifth signal, the sixth signal, and the second signal includes applying an access device activation voltage;
applying the third signal includes applying a set voltage; applying the fourth signal includes applying a first partial set voltage; applying the seventh signal includes applying a second partial set voltage; and applying the first signal includes applying a ground voltage.

5. The method of claim 4 , wherein the first partial set voltage is half of the set voltage and the second partial set voltage is half of the set voltage.

6. The method of claim 4 , wherein the first partial set voltage is ⅓ of the set voltage and the second partial set voltage is ⅔ of the set voltage.

7. The method of claim 1 , wherein applying the fifth signal, the sixth signal, and the second signal includes applying an access device activation voltage; applying the first signal includes applying a reset voltage; applying the fourth signal includes applying a first partial reset voltage; applying the seventh signal includes applying a second partial reset voltage; and applying the third signal includes applying a ground voltage.

8. The method of claim 7 , wherein the first partial reset voltage is half of the reset voltage and the second partial reset voltage is half of the reset voltage.

9. The method of claim 7 , wherein the first partial reset voltage is ⅔ of the reset voltage and the second partial reset voltage is ⅓ of the reset voltage.

10. The method of claim 1 , wherein applying the fifth signal includes applying an access device activation voltage; applying the third signal and the seventh signal includes applying a set voltage; and applying the first signal, the second signal, the fourth signal, and the sixth signal includes applying a ground voltage.

11. The method of claim 1 , wherein applying the fifth signal includes applying an access device activation voltage; applying the first signal includes applying a reset voltage; and applying the second signal, the third signal, the fourth signal, the sixth signal, and the seventh signal includes applying a ground voltage.

12. A method of operating a resistive memory device, comprising:
applying a first voltage to a selected data line coupled to a first memory cell and a second memory cell, wherein the first memory cell includes a first resistive storage element and a first access device, and wherein the second memory cell includes a second resistive storage element and a second access device; and
applying a reference voltage to a conductive line coupled to an isolation device formed between the first access device and the second access device when operating the resistive memory apparatus in a first mode;
applying a third voltage to a first select line coupled to the first resistive storage element;
applying a fourth voltage to a second select line coupled to the second resistive storage element;
applying a fifth voltage to a selected conductive line coupled to the first access device;
applying a sixth voltage to a conductive line coupled to the second access device; and
applying a seventh voltage to unselected data lines of the array.

13. The method of claim 12 , wherein the first mode of operation is a default mode of operation.

14. The method of claim 12 , wherein the method includes applying an access device activation voltage to the conductive line coupled to the isolation device formed between the first access device and the second access device when operating the resistive memory apparatus in a second mode.

15. The method of claim 14 , wherein applying the fourth voltage includes applying a portion of the third voltage and applying the seventh voltage includes applying a portion of the third voltage.

16. The method of claim 14 , wherein applying the fourth voltage includes applying a portion of the first voltage and applying the seventh voltage includes applying a portion of the first voltage.

17. The method of claim 14 , wherein the method includes operating the resistive memory apparatus in the second mode on memory cells having high current tail-bits.

18. An apparatus, comprising:
an array of memory cells; and
a controller configured to:
apply a first signal to a selected data line coupled to a first memory cell and a second memory cell, wherein the first memory cell includes a first resistive storage element and a first access device, and wherein the second memory cell includes a second resistive storage element and a second access device; and
apply a second signal to a conductive line coupled to an isolation device formed between the first access device and the second access device;
apply a third signal to a first select line coupled to the first resistive storage element;
apply a fourth signal to a second select line coupled to the second resistive storage element;
apply a fifth signal to a selected conductive line coupled to the first access device;
apply a sixth signal to a conductive line coupled to the second access device; and
apply a seventh signal to unselected data lines of the array.

19. The apparatus of claim 18 , wherein the fifth signal, the sixth signal, and the second signal is an access device activation voltage; the third signal is a set voltage; the fourth signal is a first partial set voltage; the seventh signal is a second partial set voltage; and the first signal is a ground voltage.

20. The apparatus of claim 18 , wherein the fifth signal, the sixth signal, and the second signal is an access device activation voltage; the first signal is a reset voltage; the fourth signal is a first partial reset voltage; the seventh signal is a second partial reset voltage; and the third signal is a ground voltage.

Assignees

• Micron Technology Inc

Inventors

• Liu Zengtao T
• Prall Kirk D
• Violette Mike

Classifications

• G11C2213/79

  Array wherein the access device being a transistor · CPC title

• G11C13/003

  Cell access · CPC title

• G11C13/0021

  Auxiliary circuits · CPC title

• G11C8/14

  Word line organisation; Word line lay-out · CPC title

• G11C5/063

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title