Semiconductor device and method for manufacturing same and semiconductor substrate

Patent metadata

Field	Value
Publication number	US-9373686-B2
Application number	US-201414167295-A
Country	US
Kind code	B2
Filing date	Jan 29, 2014
Priority date	Jan 30, 2013
Publication date	Jun 21, 2016
Grant date	Jun 21, 2016

Abstract

According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type made of silicon carbide; and a second semiconductor layer of a second conductivity type made of silicon carbide, placed in junction with the first semiconductor layer, and containing an electrically inactive element.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first semiconductor layer of a first conductivity type made of silicon carbide; and
a second semiconductor layer of a second conductivity type made of silicon carbide, the second semiconductor layer being provided on the first semiconductor layer, being placed injunction with the first semiconductor layer, and including an electrically inactive element contained in an upper portion of the second semiconductor layer, a basal plane dislocation being generated at an upper surface of the upper portion, and terminated in the upper portion.

2. The device according to claim 1 , wherein the element is carbon.

3. The device according to claim 1 , wherein a concentration profile of the element along stacking direction of the first semiconductor layer and the second semiconductor layer in the second semiconductor layer is maximized at a surface of the second semiconductor layer on far side from the first semiconductor layer.

4. The device according to claim 1 , wherein
the second semiconductor layer is placed on the first semiconductor layer, and
the second semiconductor layer includes:
an upper portion containing the element; and
a lower portion not containing the element.

5. The device according to claim 4 , wherein thickness of the lower portion of the second semiconductor layer is 0.5 μm or more.

6. The device according to claim 1 , wherein dose amount of the element is 1×10 11 -1×10 12 cm −2 .

7. The device according to claim 1 , wherein
the second semiconductor layer is placed on the first semiconductor layer, and
the device further comprises:
a first electrode placed below the first semiconductor layer and connected to the first semiconductor layer; and
a second electrode placed above the second semiconductor layer and connected to the second semiconductor layer.

8. The device according to claim 1 , wherein
the second semiconductor layer is placed on part of the first semiconductor layer, and
the device further comprises:
a first electrode placed on a region of the first semiconductor layer where the second semiconductor layer is not placed, the first electrode being connected to the first semiconductor layer; and
a second electrode placed on a region of the first semiconductor layer and on the second semiconductor layer, and connected to the second semiconductor layer.

9. The device according to claim 1 , wherein
the second semiconductor layer is placed on part of the first semiconductor layer, and
the device further comprises:
a third semiconductor layer of the first conductivity type placed on part of the second semiconductor layer;
a gate electrode placed immediately above a portion of the second semiconductor layer between the first semiconductor layer and the third semiconductor layer;
a gate insulating film placed between the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer on one hand and the gate electrode on the other;
a first electrode connected to the first semiconductor layer; and
a second electrode connected to the third semiconductor layer.

10. The device according to claim 1 , wherein the second semiconductor layer contains aluminum.

11. A semiconductor substrate comprising:
a first semiconductor layer of a first conductivity type made of silicon carbide; and
a second semiconductor layer of a second conductivity type made of silicon carbide, placed in junction with the first semiconductor layer, and containing an electrically inactive element.

12. The substrate according to claim 11 , wherein the element is carbon.

13. The substrate according to claim 11 , wherein a concentration profile of the element along stacking direction of the first semiconductor layer and the second semiconductor layer in the second semiconductor layer is maximized at the upper surface of the second semiconductor layer.

14. The substrate according to claim 11 , wherein a lower portion of the second semiconductor layer does not contain the element.

15. The substrate according to claim 11 , wherein the substrate is monocrystalline wafer having a diameter of 6 inches or more.

16. The substrate according to claim 11 , wherein the second semiconductor layer contains aluminum.

Assignees

• Toshiba Kk

Inventors

• Nishio Johji
• Shimizu Tatsuo
• Ota Chiharu
• Shinohe Takashi

Classifications

• H10P30/2042 Primary

  into crystalline silicon carbide · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10D8/045

  of PN junction diodes · CPC title

• H10D30/0291

  of vertical DMOS [VDMOS] FETs · CPC title

• H10D8/043

  of planar diodes · CPC title