Passivated copper chip pads

Patent metadata

Field	Value
Publication number	US-9373596-B2
Application number	US-201414307263-A
Country	US
Kind code	B2
Filing date	Jun 17, 2014
Priority date	Feb 11, 2008
Publication date	Jun 21, 2016
Grant date	Jun 21, 2016

Abstract

A structure and method of forming passivated copper chip pads is described. In various embodiments, the invention describes a substrate that includes active circuitry and metal levels disposed above the substrate. A passivation layer is disposed above a last level of the metal levels. A conductive liner is disposed in the sidewalls of an opening disposed in the passivation layer, wherein the conductive liner is also disposed over an exposed surface of the last level of the metal levels.

First claim

What is claimed is:

1. A method for forming a semiconductor component, the method comprising:
forming a cap layer over a last metal line of an inter level dielectric layer;
forming a passivation layer over the cap layer;
forming a insulating liner over the passivation layer;
forming an opening in the cap layer, the passivation layer, and the insulating liner, wherein the opening exposes a portion of the last metal line;
forming a conductive liner on surfaces of the opening by
depositing the conductive liner on the opening and over the passivation layer and the insulating liner,
depositing and patterning a photoresist layer, and
using the patterned photo resist as a mask to remove the conductive liner from over the insulating liner by using an etching process, wherein the conductive liner is removed entirely from over the insulating liner except over sidewalls of the opening, wherein the sidewalls of the conductive liner remaining after the etching process comprise a vertical section extending above a top surface of the passivation layer and a slanted section intersecting the vertical section; and

depositing an under bump metallization layer over the conductive liner.

2. The method of claim 1 , further comprising
depositing a photo resist layer over the under bump metallization layer;
patterning the photo resist layer, wherein the patterned photo resist layer exposes the under bump metallization layer on the opening;
depositing a bump metal into the patterned photo resist layer; and
reflowing the bump metal thereby forming a solder bump.

3. The method of claim 2 , wherein depositing the bump metal into the patterned photo resist layer comprises electroplating the bump metal.

4. The method of claim 2 , wherein the bump metal is deposited as layers of different compositions.

5. The method of claim 2 , wherein the solder bump comprises an eutectic 63Sn:37Pb alloy, a 5Sn:95Pb alloy, or an Sn:Ag alloy.

6. The method of claim 1 , wherein forming the opening in the cap layer and the passivation layer comprises:
depositing a photo resist layer over the passivation layer;
forming a photo mask by patterning the photo resist layer; and
etching the cap layer and the passivation layer using the photo mask as a mask layer.

7. The method of claim 1 , wherein the last metal line comprises copper.

8. The method of claim 7 , wherein the conductive liner is selected from the group consisting of Ti/TiN and Ta/TaN.

9. The method of claim 7 , wherein the conductive liner is selected from the group consisting of TiN, TaN, Ta, W and Al/Cu.

10. The method of claim 1 , wherein depositing the under bump metallization layer comprises depositing multiple layers.

11. The method of claim 10 , wherein depositing the under bump metallization layer comprises depositing layers comprising Ti/Cu/Ni.

12. A method for forming a semiconductor component, the method comprising:
forming a cap layer over a last metal line of an inter level dielectric layer;
forming a passivation layer over the cap layer;
forming an opening in the cap layer and the passivation layer, wherein the opening exposes a portion of the last metal line;
forming a conductive liner on surfaces of the opening by
depositing the conductive liner on the opening and over the passivation layer; and
removing the conductive liner from over the passivation layer, wherein the conductive liner is removed entirely from over the passivation layer except over sidewalls of the opening, wherein the sidewalls of the conductive liner remaining after the removing comprise a vertical section extending above a top surface of the passivation layer and a slanted section intersecting the vertical section; and

after removing the conductive liner, depositing an under bump metallization layer over the conductive liner.

13. A method for forming a semiconductor component, the method comprising:
forming a nitride layer over a last copper line of an inter level dielectric layer;
forming an oxide layer over the nitride layer;
forming an opening in the nitride layer and the oxide layer, wherein the opening exposes a portion of the last copper line;
forming a conductive liner on the exposed portion of the last copper line and sidewalls of the opening, wherein forming the conductive liner comprises
depositing the conductive liner on the opening and over the oxide layer,
depositing and patterning a photoresist layer, and
using the patterned photo resist as a mask to remove the conductive liner from over the nitride layer wherein the conductive liner is removed entirely from over the nitride layer except over sidewalls of the opening, wherein the sidewalls of the conductive liner remaining after being removed comprise a vertical section extending above a top surface of the oxide layer and a slanted section intersecting the vertical section;

depositing an under bump metallization layer over the conductive liner; and
depositing a bump metal over the conductive liner.

14. The method of claim 13 , wherein the conductive liner is selected from the group consisting of Ti/TiN and Ta/TaN.

15. The method of claim 13 , wherein the conductive liner is selected from the group consisting of TiN and TaN.

16. The method of claim 13 , wherein the conductive liner is selected from the group consisting of Ta, W and Al/Cu.

17. The method of claim 13 , wherein the under bump metallization layer is selected from the group consisting of Ti, Cu, Ni, Au and Cr.

18. The method of claim 13 , wherein the under bump metallization layer is selected from the group consisting of Cr—Cu and Ni—V.

19. The method of claim 13 , wherein the under bump metallization layer is selected from the group consisting of Ti—Cu, Ti—W and Ni—Au.

Assignees

• Infineon Technologies Ag

Inventors

• Goebel Thomas
• Kaltalioglu Erdem
• Naujok Markus

Classifications

• H10W72/07251

  characterised by changes in properties of the bump connectors during connecting · CPC title

• H10W72/251

  Materials · CPC title

• H10W72/012

  of bump connectors, dummy bumps or thermal bumps · CPC title

• H10W20/063

  by forming conductive members before forming protective insulating material · CPC title

• H10W72/20 Primary

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title