Enhanced patterned wafer geometry measurements based design improvements for optimal integrated chip fabrication performance

Patent metadata

Field	Value
Publication number	US-9373165-B2
Application number	US-201414520998-A
Country	US
Kind code	B2
Filing date	Oct 22, 2014
Priority date	Sep 9, 2014
Publication date	Jun 21, 2016
Grant date	Jun 21, 2016

Abstract

Methods and systems enabling ultra-high resolution topography measurements of patterned wafers are disclosed. Measurements obtained utilizing the ultra-high resolution metrology may be utilized to improve wafer metrology measurement accuracies. Additionally, measurements obtained utilizing the ultra-high resolution metrology may also be utilized to provide feedback and/or calibration control to improve fabrication and design of wafers.

First claim

What is claimed is:

1. A resolution enhancement method for wafer geometry measurements, the method comprising:
acquiring a plurality of wafer geometry images for at least one substantially identical portion of at least one wafer, wherein each of the plurality of wafer geometry images is acquired with a different sub-pixel modulation in spatial phase; and
jointly processing the plurality of wafer geometry images utilizing at least one statistical treatment to produce a resolution-enhanced representation of the plurality of wafer geometry images.

2. The method of claim 1 , wherein the at least one statistical treatment includes at least one of: a superresolution technique and a sub-pixel interpolation technique.

3. The method of claim 1 , wherein intentional shifting of an image sensor relative to the at least one wafer is utilized to provide the sub-pixel modulation in spatial phase.

4. The method of claim 1 , wherein varying at least one of: an intensity and a wavelength of an interferometer is utilized to provide the sub-pixel modulation in spatial phase.

5. The method of claim 1 , wherein the plurality of wafer geometry images are acquired by repeatedly acquiring wafer geometry images for at least one substantially identical portion of a plurality of wafers.

6. The method of claim 1 , wherein the plurality of wafer geometry images are acquired by acquiring a wafer geometry image of a wafer and obtaining the plurality of wafer geometry images representing repeating patterns present within the wafer.

7. The method of claim 1 , wherein the resolution-enhanced representation represents a resolution-enhanced topography map of the at least one portion of the at least one wafer.

8. The method of claim 7 , further comprising:
identifying at least one region within the resolution-enhanced topography map having high frequency topography variations;
determining a location for positioning at least one dummy-fill within the at least one identified region based on the at least one identified region; and
producing a modified pattern layout corresponding to the at least one wafer to include the at least one dummy-fill within the at least one identified region.

9. The method of claim 7 , further comprising:
calibrating a design simulation model at least partially based on the resolution-enhanced topography map.

10. A wafer geometry based pattern layout analysis method, the method comprising:
obtaining a first resolution-enhanced topography map for at least one portion of at least one wafer etched according to a pattern layout;
identifying at least one region within the first resolution-enhanced topography map as having high frequency topography variations;
modifying the pattern layout to include at least one dummy-fill within the at least one identified region;
obtaining a second resolution-enhanced topography map for the at least one portion of the at least one wafer etched according to the modified pattern layout;
determining an effectiveness of the modified pattern layout; and
etching a subsequent wafer based on the modified pattern layout when the modified pattern layout is determined to be effective.

11. The method of claim 10 , wherein said determining an effectiveness of the modified pattern layout further comprises:
determining whether an additional pattern layout modification is needed based on whether the second resolution-enhanced topography map has any region with high frequency topography variations.

12. The method of claim 10 , wherein obtaining a first resolution-enhanced topography map for at least one portion of at least one wafer further comprises:
acquiring a plurality of wafer geometry images for the portion of the at least one wafer, wherein each of the plurality of wafer geometry images is acquired with a different sub-pixel modulation in spatial phase; and
jointly processing the plurality of wafer geometry images utilizing at least one statistical treatment to produce the first resolution-enhanced topography map.

13. The method of claim 12 , wherein the at least one statistical treatment includes at least one of: a superresolution technique and a sub-pixel interpolation technique.

14. The method of claim 12 , wherein intentional shifting of an image sensor relative to the at least one wafer is utilized to provide the sub-pixel modulation in spatial phase.

15. The method of claim 12 , wherein varying at least one of: an intensity and a wavelength of an interferometer is utilized to provide the sub-pixel modulation in spatial phase.

16. The method of claim 12 , wherein the plurality of wafer geometry images are acquired by repeatedly acquiring wafer geometry images for at least one portion of a plurality of wafers.

17. The method of claim 12 , wherein the plurality of wafer geometry images are acquired by acquiring a wafer geometry image of a wafer and obtaining the plurality of wafer geometry images representing repeating patterns present within the wafer.

18. A wafer geometry measurement system, the system comprising:
an imaging device configured to acquire a plurality of wafer geometry images for at least one substantially identical portion of at least one wafer, wherein each of the plurality of wafer geometry images is acquired with a different sub-pixel modulation in spatial phase; and
a processor in communication with the imaging device, the processor configured to jointly process the plurality of wafer geometry images utilizing at least one statistical treatment to produce a resolution-enhanced representation of the plurality of wafer geometry images.

19. The system of claim 18 , wherein the at least one statistical treatment includes at least one of: a superresolution technique and a sub-pixel interpolation technique.

20. The system of claim 18 , wherein relative positions of the imaging device and the at least one wafer are shifted to provide the sub-pixel modulation in spatial phase.

21. The system of claim 18 , wherein at least one of: an intensity and a wavelength of an interferometer of the wafer geometry measurement system is varied to provide the sub-pixel modulation in spatial phase.

22. The system of claim 18 , wherein the imaging device acquires the plurality of wafer geometry images by repeatedly acquiring wafer geometry images for at least one substantially identical portion of a plurality of wafers.

23. The system of claim 18 , wherein the imaging device acquires the plurality of wafer geometry images by acquiring a wafer geometry image of a wafer and obtaining the plurality of wafer geometry images representing repeating patterns present within the wafer.

24. The system of claim 18 , wherein the resolution-enhanced representation represents a resolution-enhanced topography map of the at least one portion of the at least one wafer.

25. The system of claim 24 , wherein the processor is further configured to:
identify at least one region within the resolution-enhanced topography map having high frequency topography variations;
determine a location for positioning at least one dummy-fill within the at least one identified region based on the at least one identified region; and
produce a modified pattern layout corresponding to the at least one wafer to include the at least one dummy-fill within the at least one identified region.

26. The system of claim 24 , wherein the processor is further configured to:
calibrate a design simulation model at least

Assignees

• Kla Tencor Corp

Inventors

• Azordegan Amir
• Vukkadala Pradeep
• Macnaughton Craig
• Sinha Jaydeep

Classifications

• G06T2207/30148

  Semiconductor; IC; Wafer · CPC title

• G01B11/24

  for measuring contours or curvatures · CPC title

• G06F17/5081

  Physics · mapped topic

• G01N21/9501 Primary

  Semiconductor wafers (manufacturing processes per se of semiconductor devices implementing a measuring step H10P74/20) · CPC title

• G06T7/0006 Primary

  using a design-rule based approach · CPC title