Deadlock-avoiding coherent system on chip interconnect

Patent metadata

Field	Value
Publication number	US-9372808-B2
Application number	US-201314059732-A
Country	US
Kind code	B2
Filing date	Oct 22, 2013
Priority date	Oct 24, 2012
Publication date	Jun 21, 2016
Grant date	Jun 21, 2016

Abstract

This invention mitigates these deadlocking issues by a adding a separate non-blocking pipeline for snoop returns. This separate pipeline would not be blocked behind coherent requests. This invention also repartitions the master initiated traffic to move cache evictions (both with and without data) and non-coherent writes to the new non-blocking channel. This non-blocking pipeline removes the need for any coherent requests to complete before the snoop request can reach the memory controller. Repartitioning cache initiated evictions to the non-blocking pipeline prevents deadlock when snoop and eviction occur concurrently. The non-blocking channel of this invention combines snoop responses from memory controller initiated requests and master initiated evictions/non-coherent writes.

First claim

What is claimed is:

1. An interface between a multi-core shared memory controller and one of a plurality of processing cores comprising:
a read address bus adapted for receiving a read address from the processing core;
a read data bus adapted for supplying read data from the interface to the processing core;
a write address bus separate from said read address bus adapted for receiving a write address from the processing core;
a write data bus separate from said read data bus adapted for supplying write data from the processing core to the interface;
a snoop response bus adapted for supplying a snoop response signal from the processing core to the interface;
a snoop data bus separate from said read data bus and from said write data bus adapted for supplying snoop data from the processing core to the interface;
a first snoop address bus separate from said read address bus and from said write address bus adapted for supplying a snoop address from the interface to the processing core;
a command address bus adapted for supplying one of a read data address from the processing core or a write data address from the processing core to the multi-core shared memory controller;
a data bus adapted for one of (1) receiving read data from the multi-core shared memory controller, (2) supplying write data to the multi-core shared memory controller or (3) supplying snoop response data from the processing core to the multi-core shared memory controller; and
a second snoop address bus separate from said first snoop address bus adapted for receiving a snoop address from the multi-core shared memory controller.

2. The interface of claim 1 , further comprising:
a bus converter connected to said read address bus, said write address bus and said command address bus for converting said read address and said write address from the processing core from a first bus protocol to a second bus protocol supplied to said command address bus.

3. The interface of claim 1 , further comprising:
an asynchronous crossing unit connecting a first clock domain including said read address, said write address, read data, said write data, said snoop response, said snoop data and said first snoop address from the processing core to a second clock domain including said command address, said data bus and said second snoop address.

Assignees

• Texas Instruments Inc

Inventors

• Pierson Matthew D
• Wu Daniel B
• Chirca Kai

Classifications

• G06F12/0831 Primary

  using a bus scheme, e.g. with bus monitoring or watching means · CPC title

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• H04L63/0263

  Rule management · CPC title

• G06F12/0815

  Cache consistency protocols · CPC title

• G06F13/287

  Multiplexed DMA (G06F13/30 takes precedence) · CPC title