Phase control block for managing multiple clock domains in systems with frequency offsets

Patent metadata

Field	Value
Publication number	US-9106399-B2
Application number	US-201414321723-A
Country	US
Kind code	B2
Filing date	Jul 1, 2014
Priority date	Apr 4, 2006
Publication date	Aug 11, 2015
Grant date	Aug 11, 2015

Abstract

A circuit for performing clock recovery according to a received digital signal 30 . The circuit includes at least an edge sampler 105 and a data sampler 145 for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock 25 and data clock 20 signals offset in phase from one another to the respective clock inputs of the edge sampler 105 and the data sampler 145 . The clock signal supply circuit is operable to selectively vary a phase offset between the edge and data clock signals.

First claim

The invention claimed is:

1. A circuit for receiving a digital signal comprising:
at least three samplers for sampling the digital signal, each sampler having a clock input, wherein the samplers include an edge sampler and a data sampler and an adaptive sampler;
edge clock circuitry to generate an edge clock signal, coupled to the edge sampler to sample the digital signal in accordance with the edge clock signal;
data clock circuitry to generate a data clock signal, coupled to…

Assignees

• Rambus Inc

Inventors

• Lee Hae-Chang
• Zerbe Jared L
• Werner Carl William

Classifications

• H03L2207/50

  Electricity · mapped topic

• H04L7/033 Primary

  Electricity · mapped topic

• H03L7/0818

  Electricity · mapped topic

• H04L7/0087

  Electricity · mapped topic

• H04L7/0337

  Electricity · mapped topic