Selective area growth of germanium and silicon-germanium in silicon waveguides for on-chip optical interconnect applications

Patent metadata

Field	Value
Publication number	US-9368579-B2
Application number	US-201313762140-A
Country	US
Kind code	B2
Filing date	Feb 7, 2013
Priority date	Feb 7, 2012
Publication date	Jun 14, 2016
Grant date	Jun 14, 2016

Abstract

A robust fabrication process for selective area growth of semiconductors in growth windows is provided. Sidewall growth is eliminated by the presence of a spacer layer which covers the sidewalls. Undesirable exposure of the top corners of the growth windows is prevented by undercutting the growth window prior to deposition of the dielectric spacer layer. The effectiveness of this process has been demonstrated by selective-area growth of Ge and Ge/SiGe quantum wells on a silicon substrate. Integration of active optoelectronic devices with waveguide layers via end-coupling through the dielectric spacer layer can be reliably accomplished in this manner.

First claim

The invention claimed is:

1. A method for monolithic integration of dissimilar semiconductor materials, the method comprising:
providing a substrate comprising a first semiconductor layer and one or more primary protective layers disposed on the first semiconductor layer;
etching through the primary protective layers into the first semiconductor layer to provide a trench having side walls and a bottom;
laterally undercutting at least one of the protective layers by selectively etching the side walls with a side wall etch that preferentially etches the first semiconductor layer with respect to the protective layers;
forming a secondary protective layer on the side walls and bottom of the trench;
removing the secondary protective layer from the bottom of the trench with a bottom layer etch that completely removes the secondary protective layer on the bottom of the trench and does not completely remove the secondary protective layer on the side walls of the trench; and
growing a second semiconductor in the trench, wherein the first semiconductor layer and the second semiconductor have distinct compositions;
wherein the substrate comprises a silicon on insulator wafer having a buried oxide layer sandwiched between a silicon substrate and a top silicon layer;
wherein the bottom of the trench is in the top silicon layer.

2. The method of claim 1 , wherein the primary protective layers include a semiconductor waveguide layer, and wherein the semiconductor waveguide layer is optically coupled to the second semiconductor.

3. The method of claim 2 , wherein the primary protective layers include the semiconductor waveguide layer sandwiched between two waveguide cladding layers.

4. The method of claim 1 , wherein the bottom layer etch comprises an anisotropic dry etch that removes some, but not all, of the secondary protective layer on the bottom of the trench, thereby providing a remnant bottom protective layer having a thickness from 10 nm to 20 nm, followed by a wet etch that removes the remnant bottom protective layer.

5. The method of claim 1 , wherein the second semiconductor makes contact with the secondary protective layer on the side walls of the trench at one or more locations beneath the primary protective layer.

6. The method of claim 1 , wherein the growth substrate comprises a silicon on insulator substrate, an indium phosphide substrate or a gallium arsenide substrate.

7. The method of claim 1 , wherein the first semiconductor comprises silicon or indium phosphide.

8. The method of claim 1 , wherein the second semiconductor comprises germanium, a SiGe alloy, or an InGaAs alloy.

9. Apparatus comprising:
a substrate comprising a first semiconductor layer and one or more primary protective layers disposed on the first semiconductor layer;
wherein a trench is formed in the substrate that extends through the primary protective layers and at least partially through the first semiconductor layer;
wherein the trench is undercut, such that at least one of the primary protective layers laterally overhangs side walls of the trench present in the first semiconductor layer;
a secondary protective layer disposed on side walls of the trench; and
a second semiconductor formed by growth within the trench, wherein the first semiconductor layer and the second semiconductor have distinct compositions;
wherein the substrate comprises a silicon on insulator wafer having a buried oxide layer sandwiched between a silicon substrate and a top silicon layer;
wherein the bottom of the trench is in the top silicon layer.

10. The apparatus of claim 9 , wherein the apparatus is part of an optical modulator, an optical detector, or an optical source.

11. The apparatus of claim 9 , wherein the apparatus is part of an optoelectronic device integrated with a waveguide by end coupling.

12. The apparatus of claim 9 , wherein at least one of the primary protective layers laterally overhangs an interface where the second semiconductor makes contact with the secondary protective layer.

13. The apparatus of claim 9 , wherein the growth substrate comprises a silicon on insulator substrate, an indium phosphide substrate or a gallium arsenide substrate.

14. The apparatus of claim 9 , wherein the first semiconductor comprises silicon or indium phosphide.

15. The apparatus of claim 9 , wherein the second semiconductor comprises germanium, a SiGe alloy, an AlGaAs alloy, an InGaAs alloy, or an InGaAsP alloy.

Assignees

• Univ Leland Stanford Junior

Inventors

• Balram Krishna Coimbatore
• Claussen Stephanie A
• Miller David A B

Classifications

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/3248

  consisting of two layers · CPC title

• H10P14/3238

  being insulating materials · CPC title

• H10P14/3211

  Silicon, silicon germanium or germanium · CPC title

• H10P14/2905 Primary

  Silicon, silicon germanium or germanium · CPC title