Method for forming an integrated circuit package

Patent metadata

Field	Value
Publication number	US-9368183-B2
Application number	US-201313938117-A
Country	US
Kind code	B2
Filing date	Jul 9, 2013
Priority date	Jul 9, 2013
Publication date	Jun 14, 2016
Grant date	Jun 14, 2016

Abstract

An integrated circuit package includes a packaging substrate with an electrical connection pad formed thereon and an integrated circuit die coupled to the electrical connection pad. The electrical connection pad includes an electroplated surface finish layer, but does not include an electrical trace configured as a plating tail. Because the electrical connection pad is free of a plating tail, signal degradation caused by the presence of plating tails in the integrated circuit package is avoided.

First claim

I claim:

1. A method for forming an integrated circuit package, the method comprising:
depositing an electrically conductive seed layer on a packaging substrate, wherein the seed layer includes a plating tail portion and a pad portion that is in electrical communication with the plating tail portion;
depositing a mask layer on the packaging substrate to cover the plating tail portion while leaving the pad portion exposed;
after depositing the mask layer, performing an electro-plating process on the packaging substrate to deposit a metallic layer on the pad portion; and
after performing the electro-plating process, removing the mask layer and the plating tail portion.

2. The method of claim 1 , wherein removing the plating tail portion comprises exposing the plating tail portion and the metallic layer to a wet etching solution.

3. The method of claim 2 , wherein the wet etching solution is more reactive with a material included in the plating tail portion than with a material included in the metallic layer.

4. The method of claim 2 , wherein the electrically conductive seed layer comprises a copper-containing material.

5. The method of claim 4 , wherein the wet etching solution comprises at least one of an HNO 3 solution, a solution of NH 4 OH and H 2 O 2 , a solution of HNO 3 and H 2 O 2 , a solution of NH 3 and H 2 O 2 , a solution of H 3 PO 4 , HNO 3 , and CH 3 COOH, a solution of HNO 3 , H 2 SO 4 , CrO 3 , and NH 4 Cl, and a solution of HCL and FeCl 3 .

6. The method of claim 2 , further comprising, prior to depositing the electrically conductive seed layer, forming an electrical connection pad on the package substrate.

7. The method of claim 6 , wherein removing the plating tail portion further comprises exposing the electrical connection pad to a wet etching solution, wherein the electrical connection pad does not include an electroplated surface finish layer.

8. The method of claim 7 , wherein the wet etching solution is more reactive with a material included in the electrical connection pad than with a material included in the metallic layer.

9. The method of claim 1 , wherein performing an electro-plating process on the packaging substrate comprises electrically coupling the plating tail portion to an electrode.

10. The method of claim 1 , wherein depositing a mask layer on the packaging substrate comprises depositing a photoresist layer on the packaging substrate and selectively exposing portions of the photoresist layer to an energy source.

Assignees

• Nvidia Corp

Inventors

• Zhang Leilei

Classifications

• H05K3/242

  characterised by using temporary conductors on the printed circuit for electrically connecting areas which are to be electroplated · CPC title

• H05K3/067

  Etchants · CPC title

• H05K2203/175

  Configurations of connections suitable for easy deletion, e.g. modifiable circuits or temporary conductors for electroplating; Processes for deleting connections · CPC title

• G11C11/34 Primary

  using semiconductor devices · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title