Array of cross point memory cells and methods of forming an array of cross point memory cells

Patent metadata

Field	Value
Publication number	US-9362494-B2
Application number	US-201414293577-A
Country	US
Kind code	B2
Filing date	Jun 2, 2014
Priority date	Jun 2, 2014
Publication date	Jun 7, 2016
Grant date	Jun 7, 2016

Abstract

An array of cross point memory cells comprises spaced elevationally inner first lines, spaced elevationally outer second lines which cross the first lines, and a multi-resistive state region elevationally between the first and second lines where such cross. Individual of the multi-resistive state regions comprise elevationally outer multi-resistive state material and elevationally inner multi-resistive state material that are electrically coupled to one another. The inner multi-resistive state material has opposing edges in a vertical cross-section. The outer multi-resistive state material has opposing edges in the vertical cross-section that are laterally offset relative to the opposing edges of the inner multi-resistive state material in the vertical cross-section. Methods are also disclosed.

First claim

The invention claimed is:

1. A method of forming an array of cross point memory cells, comprising:
forming elevationally inner multi-resistive state material elevationally over inner conductive electrode material;
patterning the inner multi-resistive state material and the inner conductive electrode material to form spaced first lines individually comprising the inner multi-resistive state material elevationally over the inner conductive electrode material;
forming elevationally outer multi-resistive state material elevationally over and electrically coupled to the inner multi-resistive state material of the first lines;
patterning the outer multi-resistive state material to form spaced second lines that individually are elevationally over individual of the first lines, the second lines individually extending longitudinally along and individually being electrically coupled longitudinally along individual of the first lines; and
forming spaced third lines comprising outer conductive electrode material crossing elevationally over and electrically coupled to the patterned outer multi-resistive state material.

2. The method of claim 1 wherein the outer multi-resistive state material is not formed directly against the inner multi-resistive state material within the array.

3. The method of claim 1 comprising forming at least one of metal material and semi-metal material elevationally over the inner multi-resistive state material, the outer multi-resistive state material being formed after forming the at least one of metal material and semi-metal material.

4. The method of claim 3 wherein the at least one comprises metal material.

5. The method of claim 3 wherein the at least one comprises semi-metal material.

6. The method of claim 3 wherein the outer multi-resistive state material is formed elevationally over the at least one of metal material and semi-metal material, and the at least one of metal material and semi-metal material is intrinsically not capable of being programmed to multi-resistive states.

7. The method of claim 3 wherein the at least one of metal material and semi-metal material comprises lower material that is formed prior to the patterning of the inner multi-resistive state material and the inner conductive electrode material to form the first lines, and comprising forming upper material comprising at least one of metal material and semi-metal material directly against the lower material after the patterning of the inner multi-resistive state material and the inner conductive electrode material to form the first lines, the outer multi-resistive state material being formed elevationally over the upper material.

8. The method of claim 7 wherein the outer multi-resistive state material is formed directly against the upper material.

9. The method of claim 8 comprising forming the upper material to be intrinsically of higher conductivity than each of the inner and outer multi-resistive state materials when each is programmed to its highest conductivity state.

10. The method of claim 7 wherein the lower and upper materials are of different compositions.

11. The method of claim 3 comprising, prior to forming the outer multi-resistive state material:
depositing dielectric material to cover over the at least one of metal material and semi-metal material and to overfill spaces between the first lines; and
polishing the dielectric material back to expose the at least one of metal material and semi-metal material using the at least one of metal material and semi-metal material as a polish stop.

12. The method of claim 11 comprising, after the polishing, forming the outer multi-resistive state material to not be directly against the inner multi-resistive state material of individual of the first lines.

13. The method of claim 12 wherein the at least one of metal material and semi-metal material comprises lower material that is formed prior to the patterning of the inner multi-resistive state material and the inner conductive electrode material to form the first lines, and comprising forming upper material comprising at least one of metal material and semi-metal material directly against the lower material after the patterning of the inner multi-resistive state material and the inner conductive electrode material to form the first lines, the outer multi-resistive state material being formed directly against the upper material, and forming the upper material to be intrinsically of higher conductivity than each of the inner and outer multi-resistive state materials when each is programmed to its highest conductivity state.

14. The method of claim 1 comprising:
forming sacrificial material elevationally over the inner multi-resistive state material and patterning the sacrificial material, the inner multi-resistive state material, and the inner conductive electrode material to form said spaced first lines individually to comprise the sacrificial material, the inner multi-resistive state material, and the inner conductive electrode material; and
removing all of the sacrificial material before forming the elevationally outer multi-resistive state material.

15. The method of claim 1 wherein the second lines are formed to have longitudinal edges that are laterally offset from those of the first lines.

16. The method of claim 1 comprising forming select device material over the inner conductive electrode material and forming the inner multi-resistive state material over the select device material.

17. The method of claim 16 comprising forming conductive mid-electrode material over the select device material and forming the inner multi-resistive state material over the conductive mid-electrode material.

18. The method of claim 1 comprising forming conductive bottom electrode material over the inner conductive electrode material and forming the inner multi-resistive state material over the bottom conductive electrode material.

19. The method of claim 18 comprising forming conductive top electrode material over the outer multi-resistive state material and forming the outer conductive electrode material over the conductive top electrode material prior to forming the third lines.

20. A method of forming an array of cross point memory cells, comprising:
forming elevationally inner multi-resistive state material elevationally over inner conductive electrode material;
patterning the inner multi-resistive state material and the inner conductive electrode material to form spaced first lines individually comprising the inner multi-resistive state material elevationally over the inner conductive electrode material;
forming elevationally outer multi-resistive state material elevationally over and electrically coupled to the inner multi-resistive state material of the first lines;
patterning the outer multi-resistive state material to form spaced second lines that individually are elevationally over, longitudinally along, and electrically coupled to the inner multi-resistive state material of individual of the first lines;
forming spaced third lines comprising outer conductive electrode material crossing elevationally over and electrically coupled to the patterned outer multi-resistive state material; and
the outer multi-resistive state material being formed directly against the inner multi-resistive state material within the array.

21. A method of forming an array of cross point memory cells, comprising:
forming elevationally inner multi-resistive state material elevationally over inner conducti

Assignees

• Micron Technology Inc

Inventors

• Pellizzer Fabio
• Russell Stephen W
• Lindenberg Tony M

Classifications

• H01L45/1233 Primary

  Electricity · mapped topic

• H01L45/146

  Electricity · mapped topic

• H01L45/147

  Electricity · mapped topic

• H01L45/06

  Electricity · mapped topic

• H01L45/04

  Electricity · mapped topic