Low resistance LDMOS with reduced gate charge

Patent metadata

Field	Value
Publication number	US-9362398-B2
Application number	US-201113281274-A
Country	US
Kind code	B2
Filing date	Oct 25, 2011
Priority date	Oct 26, 2010
Publication date	Jun 7, 2016
Grant date	Jun 7, 2016

Abstract

An integrated circuit containing an MOS transistor with a drain drift region adjacent to the channel region, a field oxide element in the drain region, a first gate section over the channel region and a second gate section over the field oxide element, with a gap between the gate sections so that at least half of the drift region is not covered by gate. A process of forming an integrated circuit containing an MOS transistor with a drain drift region adjacent to the channel region, a field oxide element in the drain region, a first gate section over the channel region and a second gate section over the field oxide element, with a gap between the gate sections so that at least half of the drift region is not covered by gate, so that the source/drain implant is blocked from the drift region below the gap.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a metal oxide semiconductor (MOS) transistor with a drain region adjacent to a channel region of said MOS transistor, said MOS transistor including:
a drain insulator in said drain region between said channel region and a drain contact region in said drain region, so that said drain region extends under said drain insulator;
a drift region in the drain region between the channel region and the drain insulator;
a gate, said gate including:
a first gate section over said channel region; and
a second gate section over said drain insulator such that the second gate section does not overlap the drift region;
the first gate section dimensioned such that at least half of said drift region is not covered by said gate; and
an implant blocking section between said first gate section and said second gate section, said implant blocking section being formed of gate sidewall material on lateral surfaces of said first gate section and said second gate section.

2. The integrated circuit of claim 1 , in which said MOS transistor is n-channel.

3. The integrated circuit of claim 1 , in which said MOS transistor is p-channel.

4. The integrated circuit of claim 1 , in which said first gate section is not connected to said second gate section by any gate material over said drift region.

5. An integrated circuit, comprising:
an MOS transistor with a drain region adjacent to a channel region of said MOS transistor, said MOS transistor including:
a drain insulator in said drain region between said channel region and a drain contact region in said drain region, so that said drain region extends under said drain insulator;
a drift region in the drain region between the channel region and the drain insulator; and
a gate, said gate including:
a first gate section over said channel region and overlapping said drain region;
a second gate section over said drain insulator; and

two or more gate connecting elements each connecting said first and second gate sections, said gate connecting elements being formed of a same material as said first gate section and said second gate section;
the first gate section dimensioned such that at least half of said drift region is not covered by said gate; and
an implant blocking section between said first gate section and said second gate section, said implant blocking section being formed of gate sidewall material on lateral surfaces of said first gate section and said second gate section.

6. The integrated circuit of claim 5 , in which each said gate connecting element is separated from immediately adjacent gate connecting elements by less than 2 microns.

7. The integrated circuit of claim 5 , in which said MOS transistor is n-channel.

8. The integrated circuit of claim 5 , in which said MOS transistor is p-channel.

9. The integrated circuit of claim 5 , in which said second gate section does not overlap said drift region.

Assignees

• Pendharkar Sameer P
• Texas Instruments Inc

Inventors

• Pendharkar Sameer P

Classifications

• H10D30/603 Primary

  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS] · CPC title

• H10D64/519

  characterised by their top-view geometrical layouts · CPC title

• H10D64/111

  Field plates · CPC title

• H10D62/116

  adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions · CPC title

• H10D30/0221

  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS] · CPC title