Two-tier defect scan management
US-2024402922-A1 · Dec 5, 2024 · US
US8988940B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8988940-B2 |
| Application number | US-201213562667-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 31, 2012 |
| Priority date | Jul 31, 2012 |
| Publication date | Mar 24, 2015 |
| Grant date | Mar 24, 2015 |
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Embodiments of the present invention provide a memory array of macro cells. Each macro cell comprises a storage element and a calibration element. The storage element and its corresponding calibration element are part of a common memory array within an integrated circuit, and therefore, are in close proximity to each other. The calibration element may store a parameter used to modify the threshold voltage of the storage element.
Opening claim text (preview).
What is claimed is: 1. An electronic circuit comprising: a plurality of flash memory cells, wherein: the plurality of flash memory cells comprises a storage flash cell and a calibration flash cell; the calibration flash cell is electrically connected to the storage flash cell; the storage flash cell and calibration flash cell comprise a macro cell; the storage flash cell is configured and disposed to store data; and the calibration flash cell is configured and disposed to…
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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