Fabric multipathing based on dynamic latency-based calculations

Patent metadata

Field	Value
Publication number	US-9360885-B2
Application number	US-201313859651-A
Country	US
Kind code	B2
Filing date	Apr 9, 2013
Priority date	Apr 9, 2013
Publication date	Jun 7, 2016
Grant date	Jun 7, 2016

Abstract

In one embodiment, a system for determining latency in paths includes logic integrated with and/or executable by a processor, the logic being adapted to synchronize clocks of two devices connected via two or more link aggregation (LAG) ports and/or multiple devices within paths through a network fabric, determine a transit delay for each LAG port and/or path, store the transit delay for each LAG port to a LAG structure along with an identifier for the LAG port and/or for each path to an equal cost multi-path (ECMP) structure along with an identifier of the path, sort the LAG ports according to each LAG port's transit delay and mark a LAG port having the lowest latency, and sort the paths according to each path's transit delay and mark a path having the lowest latency, wherein each path has an equal path cost factor.

First claim

What is claimed is:

1. A system comprising logic integrated with a processor, the logic being configured to:
synchronize clocks of two intermediate devices across a plurality of link aggregation (LAG) ports 1 to N therebetween, wherein N is at least 2, and wherein the clock synchronization is performed independently across each of the LAG ports;
determine a latency for each LAG port based on information derived from synchronizing the clocks of the two intermediate devices;
store the latency for each LAG port to a LAG structure along with an identifier of a corresponding LAG port and mark a LAG port having a lowest latency;
discover a configuration of a network fabric after determining the latency for each LAG port;
synchronize clocks of two devices across a plurality of paths 1 to P connecting the two devices through the network fabric, wherein P is at least 2, wherein each path has an equal path cost factor, and wherein the clock synchronization is performed independently across the plurality of paths connecting the two devices in the network fabric;
determine a transit delay for each path of the plurality of paths connecting the two devices in the network fabric based on information derived from synchronizing the clocks of the two devices and the latency for LAG ports included in the plurality of paths;
store the transit delay for each path of the plurality of paths connecting the two devices in the network fabric to an equal cost multi-path (ECMP) structure along with an identifier for each path of the plurality of paths connecting the two devices in the network fabric;
and sort the plurality of paths connecting the two devices in the network fabric in the ECMP structure according to each path's transit delay and mark a path having a lowest latency.

2. The system as recited in claim 1 , wherein the clock synchronization is performed via Institute of Electrical and Electronics Engineers (IEEE) standard 1588-2002 and/or 1588-2008.

3. The system as recited in claim 1 , wherein the logic is further configured to determine an offset between clocks of the two devices across each path of the plurality of paths and an offset between clocks of intermediate devices and a source device in each path of the plurality of paths connecting the two devices in the network fabric, wherein latency is based on transit delay determined during the clock synchronization.

4. The system as recited in claim 3 , wherein the logic is further configured to:
cause a first device to send a synchronization message to a second device at a first time, T(M)(1), across each path of the plurality of paths connecting the two devices in the network fabric;
determine a second time, T(S)(2), at which each synchronization message is received at the second device across each path of the plurality of paths connecting the two devices in the network fabric; and
calculate a difference between the second time and the first time, such that Offset=T(S)(2)−T(M)(1), for each path of the plurality of paths connecting the two devices in the network fabric.

5. The system as recited in claim 4 , wherein the logic is further configured to determine the offset between clocks of the two devices across each path of the plurality of paths periodically by:
causing the first device to send a follow-up message to the second device at a third time, T(M)(3), across each path of the plurality of paths;
determining a fourth time, T(S)(4), at which each follow-up message is received at the second device across each path of the plurality of paths; and
calculating a difference between the fourth time and the third time, such that Offset=T(S)(4)−T(M)(3), for each path of the plurality of paths.

6. The system as recited in claim 1 , wherein the transit delay for each path connecting the two devices in the network fabric is determined every tenth of a second, and wherein the path having the lowest latency is updated in response to determining the transit delay for each path of the plurality of paths connecting the two devices in the network fabric.

7. The system as recited in claim 1 , wherein the logic is further configured to:
receive a packet;
determine whether the packet demands low latency service;
forward the packet using the path marked as having the lowest latency in response to a determination that the packet demands low latency service; and
choose a path to forward the packet other than the path marked as having the lowest latency in response to a determination that the packet does not demand low latency service.

8. A method comprising:
a processor synchronizing clocks of two intermediate devices across a plurality of link aggregation (LAG) ports 1 to N therebetween, wherein N is at least 2, and wherein the clock synchronization is performed independently across each of the LAG ports;
determining a latency for each LAG port based on information derived from synchronizing the clocks of the two intermediate devices;
storing the latency for each LAG port to a LAG structure along with an identifier of a corresponding LAG port and mark a LAG port having a lowest latency;
discovering a configuration of a network fabric after determining the latency for each LAG port;
the processor synchronizing a first clock of a first device and a second clock of a second device across a plurality of paths connecting the first device with the second device through a network fabric, wherein the first clock and the second clock are synchronized independently across the paths connecting the first device with the second device, including independently across each link aggregation (LAG) port of at least one (LAG) included in at least one of the paths connecting the first device with the second device;
determining a latency for each path of the plurality of paths connecting the first device with the second device in the network fabric based on information derived from synchronizing the first and second clocks and the latency for LAG ports included in the plurality of paths;
the processor storing the latency for each path of the plurality of paths connecting the first device with the second device in the network fabric to an equal cost multi-path (ECMP) structure along with an identifier for each path of the plurality of paths connecting the first device with the second device in the network fabric; and
the processor sorting the plurality of paths according to each path's latency and marking a path having a lowest latency.

9. The method as recited in claim 8 , wherein the clock synchronization is performed via Institute of Electrical and Electronics Engineers (IEEE) standard 1588-2002 or 1588-2008.

10. The method as recited in claim 8 , wherein the clock synchronization comprises:
the processor determining an offset between the first clock and the second clock across each path of the plurality of paths connecting the first device with the second device in the network fabric; and
the processor determining a transit delay for each path of the plurality of paths connecting the first device with the second device in the network fabric,
wherein the latency for each path of the plurality of paths connecting the first device with the second device in the network fabric is based on the transit delay for the path.

11. The method as recited in claim 10 , wherein the first clock acts as a master clock in the clock synchronization.

12. The method as recited in claim 10 , wherein a clock source having a stratum of zero or one acts as a master clock in the clock synchronization.

13. The method as recited in claim 10 , wherein the offset between the first clock and the second clock is determined for each path of the plurality of

Assignees

• IBM

Inventors

• Ilyas Talha J
• Kamble Keshav G
• Pandey Vijoy A

Classifications

• G06F1/1603

  Arrangements to protect the display from incident light, e.g. hoods · CPC title

• G06F1/1601

  Constructional details related to the housing of computer displays, e.g. of CRT monitors, of flat displays (constructional details related to flat displays integrated in a portable computer, e.g. laptop, handheld computer G06F1/1637; constructional details related to television receivers H04N5/64) · CPC title

• G06F1/12 Primary

  Synchronisation of different clock signals {provided by a plurality of clock generators} · CPC title

• H04J3/0667

  Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays (arrangements for monitoring round trip delays in packet switching networks H04L43/0864) · CPC title

• H04L45/20

  Hop count for routing purposes, e.g. TTL · CPC title