Circuit for clamping current in a charge pump

Patent metadata

Field	Value
Publication number	US-9360878-B2
Application number	US-201414513006-A
Country	US
Kind code	B2
Filing date	Oct 13, 2014
Priority date	Nov 30, 2006
Publication date	Jun 7, 2016
Grant date	Jun 7, 2016

Abstract

A circuit for clamping current in a charge pump is disclosed. The charge pump includes switching circuitry having a number of switching circuitry transistors. Each of first and second pairs of transistors in the circuit can provide an additional path for current from its associated one of the switching circuitry transistors during off-switching of that transistor so that a spike in current from the switching circuitry transistor is only partially transmitted through a path extending between the switching circuitry transistor and a capacitor of the charge pump.

First claim

What is claimed is:

1. A charge pump comprising:
a plurality of transistors;
at least one capacitor;
a first path configured to communicate current with the at least one capacitor, wherein a first transistor of the plurality of transistors is located on the first path and generates a first temporary parasitic spike in current when the first transistor switches off in response to a control signal changing from a first value to a second value; and
a current clamping circuit configured to:
open an additional path for current from the first transistor when the control signal changes from the first value to the second value such that the first temporary parasitic spike is only partially communicated through the first path; and
close the additional path after the additional path has been open for a period of time and the first temporary parasitic spike has dissipated.

2. The charge pump of claim 1 , further comprising a second path configured to communicate current with the at least one capacitor, wherein a second transistor of the plurality of transistors is located on the second path and generates a second temporary parasitic spike in current when the second transistor switches off in response to a second control signal changing from the second value to the first value.

3. The charge pump of claim 1 , wherein the first path further comprises a second transistor coupled between the first transistor and the at least one capacitor, the second transistor having a gate coupled to a first bias input.

4. The charge pump of claim 3 , wherein the current clamping circuit comprises a third transistor coupled between the first bias input and the first transistor.

5. The charge pump of claim 4 , wherein the current clamping circuit further comprises at least one inverter coupled between the control signal and a gate of the third transistor.

6. The charge pump of claim 1 , wherein the current clamping circuit comprises a PMOS transistor and an NMOS transistor each having a gate coupled to receive the control signal, wherein the PMOS and NMOS transistor are coupled in series with the first transistor.

7. The charge pump of claim 1 , wherein the current clamping circuit comprises an analogue repeater with an input coupled to the at least one capacitor.

8. The charge pump of claim 7 , wherein the current clamping circuit further comprises a second transistor having a gate coupled to receive the control signal and wherein the second transistor is coupled between the first transistor and the output of the analogue repeater.

9. The charge pump of claim 8 , wherein the current clamping circuit further comprises one or more inverters coupled between the control signal and the gate of the second transistor.

10. A method of operating a charge pump, the method comprising:
switching off a first transistor of the charge pump in response to a control signal changing from a first value to a second value, the first transistor located on a first path of the charge pump that is configured to communicate current with at least one capacitor of the charge pump, wherein the switching off of the first transistor generates a first temporary parasitic spike in current;
opening an additional path for current from the first transistor in response to the control signal changing from the first value to the second value such that the first temporary parasitic spike is only partially communicated through the first path; and
closing the additional path after the additional path has been open for a period of time and the first temporary parasitic spike has dissipated.

11. The method of claim 10 , further comprising:
switching off a second transistor of the charge pump in response to a second control signal changing from the second value to the first value, the second transistor located on a second path of the charge pump that is configured to communicate current with the at least one capacitor of the charge pump, wherein the switching off of the second transistor generates a second temporary parasitic spike in current;
opening a second additional path for current from the second transistor in response to the control signal changing from the second value to the first value such that the second temporary parasitic spike is only partially communicated through the first path; and
closing the second additional path after the second additional path has been open for a second period of time and the second temporary parasitic spike has dissipated.

12. The method of claim 10 , wherein the first path further comprises a second transistor coupled between the first transistor and the at least one capacitor, the second transistor having a gate coupled to a first bias input.

13. The method of claim 12 , wherein the additional path is opened and closed by a current clamping circuit that comprises a third transistor coupled between the first bias input and the first transistor.

14. The method of claim 13 , wherein the current clamping circuit further comprises at least one inverter coupled between the control signal and a gate of the third transistor.

15. The method of claim 10 , wherein the additional path is opened and closed by a current clamping circuit that comprises a PMOS transistor and an NMOS transistor each having a gate coupled to receive the control signal, wherein the PMOS and NMOS transistor are coupled in series with the first transistor.

16. The method of claim 10 , wherein the additional path is opened and closed by a current clamping circuit that comprises an analogue repeater with an input coupled to the at least one capacitor.

17. The method of claim 16 , wherein the current clamping circuit further comprises a second transistor having a gate coupled to receive the control signal and wherein the second transistor is coupled between the first transistor and the output of the analogue repeater.

18. The method of claim 17 , wherein the current clamping circuit further comprises one or more inverters coupled between the control signal and the gate of the second transistor.

Assignees

• Conversant Intellectual Property Man Inc

Inventors

• Vlasenko Peter
• Mai Huy Tuong

Classifications

• H03L7/0895

  Details of the current generators (H03L7/0893 takes precedence) · CPC title

• G05F3/02

  Regulating voltage or current · CPC title

• G05F1/625 Primary

  wherein it is irrelevant whether the variable actually regulated is AC or DC · CPC title

• H03K5/086

  generated by feedback · CPC title

• H02M3/073

  Charge pumps of the Schenkel-type · CPC title