Bonding of heterogeneous material grown on silicon to a silicon photonic circuit

Patent metadata

Field	Value
Publication number	US-9360623-B2
Application number	US-201414577938-A
Country	US
Kind code	B2
Filing date	Dec 19, 2014
Priority date	Dec 20, 2013
Publication date	Jun 7, 2016
Grant date	Jun 7, 2016

Abstract

A method of fabricating a heterogeneous semiconductor wafer includes depositing a III-V type semiconductor epitaxial layer on a first wafer having a semiconductor substrate. The first wafer is then bonded to a second wafer having a patterned silicon layer formed on a semiconductor substrate, wherein the III-V type semiconductor epitaxial layer is bonded to the patterned silicon layer of the second wafer. The semiconductor substrate associated with the first wafer is removed to expose the III-V type semiconductor epitaxial layer.

First claim

The invention claimed is:

1. A method of fabricating a heterogeneous semiconductor wafer, the method comprising:
depositing a III-V type semiconductor epitaxial layer on a first wafer having a semiconductor substrate;
bonding the first wafer to a second wafer having a patterned silicon layer formed on a semiconductor substrate, wherein the III-V type semiconductor epitaxial layer is bonded to the patterned silicon layer of the second wafer, and wherein the second wafer includes a metal layer that includes a thin contact metal stack on top of the patterned silicon layer, and wherein bonding includes annealing under pressure to form covalent bonds between the patterned silicon layer and the III-V type semiconductor epitaxial layer and interdiffusion between the thin contact metal stack and the III-V type semiconductor epitaxial layer; and
removing the semiconductor substrate associated with the first wafer to expose the III-V type semiconductor epitaxial layer.

2. The method of claim 1 , further including:
depositing a buffer layer on the semiconductor substrate associated with the first wafer, wherein the III-V type semiconductor epitaxial layer is deposited on the buffer layer.

3. The method of claim 1 , wherein the buffer layer comprises one or more of Germanium (Ge), Silicon Germanium (SiGe), Strontium Titanate (SrTO 3 ), and Silicon Dioxide (SiO 2 ).

4. The method of claim 1 , wherein the III-V type semiconductor epitaxial layer comprises one or more of quantum dots, quantum wells, quantum wires, quantum dashes.

5. The method of claim 1 , further including:
processing the exposed III-V type semiconductor epitaxial layer following removal of the semiconductor substrate to form one or more active optoelectronic devices coupled to the patterned silicon layer.

6. The method of claim 5 , wherein the one or more active optoelectronic devices includes one or more laser, photodetector, modulator, phase tuning element, interferometric device, wavelength multiplexer, polarization splitter, coupler, or saturable absorber.

7. The method of claim 5 , wherein the patterned silicon layer includes one or more passive optical components coupled to the one or more active optoelectronic devices formed within the III-V type semiconductor epitaxial layer.

8. The method of claim 7 , wherein the passive optical components include one or more of waveguides, filters, and/or splitters.

9. The method of claim 1 , wherein the second wafer is a silicon-on-insulator wafer that includes a silicon substrate, a buried oxide layer deposited on the silicon substrate, and the patterned silicon layer formed on the buried oxide layer.

10. The method of claim 1 , wherein bonding the first wafer to the second wafer includes providing electrical conductivity between the patterned silicon layer and the III-V type semiconductor epitaxial layer.

11. The method of claim 1 , wherein the bonding process is selected from the group consisting of: hydrophilic bonding, hydrophobic bonding, plasma assisted bonding, solder bonding, metal bonding, and polymer bonding (e.g., benzocyclobutene bonding).

12. The method of claim 1 , wherein the semiconductor substrates associated with the first and second wafers, respectively, are silicon substrates.

13. The method of claim 2 , further including depositing a release layer on the buffer layer prior to depositing the III-V type semiconductor epitaxial layer.

14. The method of claim 13 , further including selectively etching the release layer positioned between the buffer layer and the III-V epitaxial layer to separate the buffer layer and the silicon substrate from the III-V epitaxial layer.

Assignees

• Univ California

Inventors

• Bowers John E
• Bovington Jock

Classifications

• G02B6/131 Primary

  by using epitaxial growth (epitaxial growth for semiconductors H10P14/20) · CPC title

• G02B6/12002 Primary

  Three-dimensional structures · CPC title