ESD clamp for multiple power rails

Patent metadata

Field	Value
Publication number	US-9356443-B2
Application number	US-201213563420-A
Country	US
Kind code	B2
Filing date	Jul 31, 2012
Priority date	Jul 31, 2012
Publication date	May 31, 2016
Grant date	May 31, 2016

Abstract

An Electrostatic Discharge (ESD) clamp includes first power rail, a second power rail separate from the first power rail, and an ESD discharging circuit including a plurality of cascaded MOS transistors coupled between the second power rail and an electrical ground. A bias circuit is configured to turn on the ESD discharging circuit in response to an ESD event on the second power rail, and to turn off the ESD discharging circuit during a normal operation of the ESD clamp.

First claim

What is claimed is:

1. An Electrostatic Discharge (ESD) clamp comprising:
a first power rail;
a second power rail separate from the first power rail;
a first switch transistor coupling the first power rail to the second power rail;
an ESD discharging circuit comprising a plurality of cascaded MOS transistors coupled between the second power rail and an electrical ground; and
a bias circuit configured to turn on the ESD discharging circuit in response to an ESD event on the second power rail, and to turn off the ESD discharging circuit during a normal operation of the ESD clamp, the bias circuit comprising a first control signal generator, wherein the first control signal generator comprises:
a first and a second NMOS transistor; and
a first and a second PMOS transistor cascaded with the first and the second NMOS transistors, wherein gates of the second NMOS transistor and the first and the second PMOS transistors are connected to the first power rail.

2. The ESD clamp of claim 1 ,
wherein the first control signal generator is configured to turn on the first switch transistor and one of the plurality of cascaded MOS transistors during the ESD event, and to turn off the first switch transistor and the one of the plurality of cascaded MOS transistors during the normal operation of the ESD clamp.

3. The ESD clamp of claim 2 further comprising:
a third power rail separated from the first and the second power rails;
a second switch transistor coupling the second power rail to the third power rail; and
a second control signal generator, wherein the second control signal generator is configured to turn on the second switch transistor and an additional one of the plurality of cascaded MOS transistors during the ESD event, and to turn off the second switch transistor and the additional one of the plurality of cascaded MOS transistors during the normal operation.

4. The ESD clamp of claim 1 , wherein a gate of the first NMOS transistor is configured to receive an output signal from an ESD detector.

5. The ESD clamp of claim 4 , wherein the ESD detector comprises a resistor and a capacitor coupled in series between the first power rail and the electrical ground.

6. The ESD clamp of claim 1 , wherein the plurality of cascaded MOS transistors in the ESD discharging circuit comprises PMOS transistors.

7. The ESD clamp of claim 1 , wherein the first and the second power rails are coupled to a first output and a second output, respectively, of a voltage source, wherein the voltage source is configured to output a first power supply voltage to the first power rail, and a second power supply voltage to the second power rail, and wherein the second power supply voltage is higher than the first power supply voltage.

8. A Electrostatic Discharge (ESD) clamp comprising:
a first power rail;
a second power rail separated from the first power rail;
an ESD discharging circuit comprising a plurality of cascaded MOS transistors cascaded from the second power rail to an electrical ground (VSS); and
a bias circuit coupled to the ESD discharging circuit, wherein the bias circuit comprises:
a first NMOS transistor comprising a first source coupled to VSS; and
a second NMOS transistor comprising a source connected to a drain of the first NMOS transistor;
a first PMOS transistor comprising a drain connected to a drain of the second NMOS transistor; and
a second PMOS transistor comprising a drain connected to a source of the first PMOS transistor, and a source connected to the second power rail, wherein gates of the second NMOS transistor, the first PMOS transistor, and the second PMOS transistor are further connected to the first power rail.

9. The ESD clamp of claim 8 further comprising:
an ESD detector configured to detect an ESD transient on the first power rail; and
an inverter comprising an input coupled to an output of the ESD detector, and an output coupled to a gate of the first NMOS transistor.

10. The ESD clamp of claim 9 , wherein the ESD detector comprises:
a capacitor comprising a first end coupled to the VSS; and
a resistor coupling a second end of the capacitor to the first power rail, wherein the input of the inverter is coupled to the second end of the capacitor.

11. The ESD clamp of claim 8 further comprising a switch transistor comprising a first source/drain coupled to second power rail, and a second source/drain coupled to the first power rail.

12. The ESD clamp of claim 11 , wherein a gate of the switch transistor is coupled to a drain of the first PMOS transistor.

13. The ESD clamp of claim 8 , wherein a drain of the first PMOS transistor is coupled to a gate of one of the plurality of cascaded MOS transistors.

14. The ESD clamp of claim 8 , wherein the plurality of cascaded MOS transistors comprises PMOS transistors.

15. A method comprising:
in response to an Electrostatic Discharge (ESD) event on a second power rail, conducting an ESD voltage from the second power rail to a first power rail through a switch transistor, wherein the second power rail carries a second power supply voltage higher than a first power supply voltage on the first power rail;
detecting the ESD voltage on the first power rail to generate a detection signal, wherein the detection signal is a logic low signal;
using the detection signal to turn on a first MOS transistor in an ESD discharging circuit, wherein the ESD discharging circuit comprises a plurality of MOS transistors cascaded between the second power rail and an electrical ground, wherein each of the plurality of MOS transistors is a PMOS transistor;
using the detection signal and the ESD voltage on the first power rail to generate a control signal; and
using the control signal to turn on a second MOS transistor in the ESD discharging circuit, wherein the first and the second MOS transistors are cascaded.

16. The method of claim 15 , further comprising providing the control signal back to a gate of the switch transistor to keep the switch transistor turned on during the ESD event.

17. The method of claim 16 further comprising, in response to non-ESD events, generating an additional control signal to turn off the switch transistor.

18. The method of claim 17 further comprising, in response to the non-ESD events, using the additional control signal to turn off the ESD discharging circuit.

Assignees

• Yang Tsung-Ju
• Taiwan Semiconductor Mfg

Inventors

• Yang Tsung-Ju

Classifications

• H02H9/046 Primary

  responsive to excess voltage appearing at terminals of integrated circuits · CPC title