Techniques for forming contacts to quantum well transistors

Patent metadata

Field	Value
Publication number	US-9356099-B2
Application number	US-201414334636-A
Country	US
Kind code	B2
Filing date	Jul 17, 2014
Priority date	Dec 23, 2009
Publication date	May 31, 2016
Grant date	May 31, 2016

Abstract

Techniques are disclosed for providing a low resistance self-aligned contacts to devices formed in a semiconductor heterostructure. The techniques can be used, for example, for forming contacts to the gate, source and drain regions of a quantum well transistor fabricated in III-V and SiGe/Ge material systems. Unlike conventional contact process flows which result in a relatively large space between the source/drain contacts to gate, the resulting source and drain contacts provided by the techniques described herein are self-aligned, in that each contact is aligned to the gate electrode and isolated therefrom via spacer material.

First claim

What is claimed is:

1. A semiconductor device comprising:
a quantum well structure disposed above a substrate, said quantum well structure having an upper barrier layer above a quantum well layer;
a trench, through said upper barrier layer disposed in said quantum well structure, and above said quantum well layer, said trench having sidewalls and a bottom;
source/drain metal regions disposed on the quantum well structure and on either side of said trench;
a gate electrode disposed in said trench;
a gate dielectric layer on the bottom of said trench and between said gate electrode and said quantum well structure; and
a dielectric material on the sidewalls of said trench and extending to the bottom of said trench, wherein said dielectric material is between said gate electrode and said source/drain metal regions, and between the sidewalls of said trench and said gate dielectric layer.

2. The semiconductor device of claim 1 , wherein said gate dielectric layer is a high-k gate dielectric layer.

3. The semiconductor device of claim 1 , wherein said quantum well structure comprises a bottom barrier layer, said quantum well layer disposed above said bottom barrier layer, a semiconductor spacer layer above said quantum well layer, a doping layer above said quantum well layer, and a contact layer above said upper said barrier layer wherein said source/drain metal regions are disposed on said contact layer.

4. The semiconductor device of claim 3 , wherein said bottom of said trench is in said doping layer.

5. The semiconductor device of claim 3 , wherein said bottom of said trench is in said semiconductor spacer layer.

6. The semiconductor device of claim 3 , further comprising an etch stop layer.

7. The semiconductor device of claim 6 , wherein said etch stop layer is InP.

8. A semiconductor device comprising:
a quantum well structure disposed above a substrate, said quantum well structure having an upper barrier layer above a quantum well layer;
a trench, through said upper barrier layer disposed in said quantum well structure, and above said quantum well layer, said trench having sidewalls and a bottom;
source/drain metal regions disposed on the quantum well structure and on either side of said trench;
a gate electrode disposed in said trench;
a gate dielectric layer on the bottom of said trench and between said gate electrode and said quantum well structure; and
a dielectric material on the sidewalls of said trench and extending to the bottom of said trench, wherein said dielectric material is between said gate electrode and said source/drain metal regions where said gate electrode is laterally adjacent to said source/drain metal regions, and wherein said dielectric material is disposed on a portion of said gate dielectric layer.

9. The semiconductor device of claim 8 , wherein said gate dielectric layer is a high-k gate dielectric layer.

10. The semiconductor device of claim 8 , wherein said quantum well structure comprises a bottom barrier layer, said quantum well layer disposed above said bottom barrier layer, a semiconductor spacer layer above said quantum well layer, a doping layer above said quantum well layer, and a contact layer above said upper said barrier layer wherein said source/drain metal regions are disposed on said contact layer.

11. The semiconductor device of claim 10 , wherein said bottom of said trench is in said doping layer.

12. The semiconductor device of claim 10 , wherein said bottom of said trench is in said semiconductor spacer layer.

13. The semiconductor device of claim 10 , further comprising an etch stop layer.

14. The semiconductor device of claim 13 , wherein said etch stop layer is InP.

15. An integrated circuit device, comprising:
a substrate;
a buffer layer above the substrate;
a quantum well channel layer above the buffer layer, the quantum well channel layer comprising In, Ga and As;
a semiconductor contact layer above the quantum well channel layer, the semiconductor contact layer comprising In and As;
a metal layer directly on the semiconductor contact layer;
a gate trench through the metal layer and through the semiconductor contact layer defining source and drain metal contacts and semiconductor source and drain regions directly at respective sides of the gate trench, said gate trench having a bottom and walls;
a dielectric spacer material on the walls of the gate trench and extending to the bottom of said gate trench, wherein the dielectric spacer material is a nitride;
a gate dielectric layer on the bottom of said gate trench, wherein said gate dielectric layer is a high-k dielectric layer comprising aluminum oxide, and wherein said gate dielectric layer is between and laterally adjacent to the dielectric spacer material at the bottom of the gate trench; and
a gate material on the gate dielectric in the gate trench for a gate electrode, the gate material comprising a metal.

Assignees

• Pillarisetty Ravi
• Chu-Kung Benjamin
• Hudait Mantu K
• Radosavljevic Marko
• Kavalieros Jack T
• Rachmady Willy
• Mukherjee Niloy
• Chau Robert S
• Intel Corp

Inventors

• Pillarisetty Ravi
• Chu-Kung Benjamin
• Hudait Mantu K
• Radosavljevic Marko
• Kavalieros Jack T
• Rachmady Willy
• Mukherjee Niloy
• Chau Robert S

Classifications

• H10D64/691

  comprising metallic compounds, e.g. metal oxides or metal silicates  (insulators comprising nitrogen H10D64/693) · CPC title

• H10D64/411

  for FETs · CPC title

• H10D64/513

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title

• H10D64/258

  characterised by the relative positions of the source or drain electrodes with respect to the gate electrode · CPC title

• H10D64/251

  Source or drain electrodes for field-effect devices · CPC title