BSI image sensor chips and methods for forming the same

Patent metadata

Field	Value
Publication number	US-9356059-B2
Application number	US-201213352980-A
Country	US
Kind code	B2
Filing date	Jan 18, 2012
Priority date	Dec 15, 2011
Publication date	May 31, 2016
Grant date	May 31, 2016

Abstract

A device includes semiconductor substrate having a front side and a backside. A polysilicon layer is disposed on the backside of the semiconductor substrate. The polysilicon layer includes a portion doped with a p-type impurity. A dielectric layer is disposed on the backside of the semiconductor substrate, wherein the polysilicon layer is between the semiconductor substrate and the polysilicon layer.

First claim

What is claimed is:

1. A device comprising:
a semiconductor substrate comprising a front side and a backside;
a metal pad in a metallization layer and on the front side of the semiconductor substrate;
a polysilicon layer on the backside of the semiconductor substrate, wherein the polysilicon layer comprises:
a bottom layer;
a middle layer; and
an upper layer, wherein the middle layer is between the bottom layer and the upper layer, wherein the middle layer is doped with a p-type impurity having a first concentration, and wherein second concentrations of the p-type impurity in the bottom layer and the upper layer are lower than the first concentration;

a dielectric layer on the backside of the semiconductor substrate, wherein the polysilicon layer is between the semiconductor substrate and the dielectric layer;
a recess extending from a back surface of the semiconductor substrate to penetrate through the semiconductor substrate, wherein the polysilicon layer extends to an edge of the recess; and
an electrical pad extending into the recess, wherein the electrical pad contacts the metal pad on the front side of the semiconductor substrate.

2. The device of claim 1 further comprising a first image sensor disposed on the front side of the semiconductor substrate.

3. The device of claim 2 further comprising:
a second image sensor disposed on the front side of the semiconductor substrate; and
a metal shielding layer over and aligned to the first image sensor, wherein the second image sensor is not aligned to the metal shielding layer, and wherein the polysilicon layer is between the metal shielding layer and the semiconductor substrate, and is aligned to the first image sensor and the second image sensor, and the dielectric layer is between the metal shielding layer and the polysilicon layer, and the dielectric layer extends beyond opposite sidewalls of the metal shielding layer.

4. The device of claim 1 further comprising an oxide layer between and contacting a back surface of the semiconductor substrate and the polysilicon layer, wherein the oxide layer comprises an oxide of the material of the semiconductor substrate.

5. The device of claim 1 , wherein the bottom layer and the upper layer are substantially free from the p-type impurity.

6. The device of claim 1 , wherein the electrical pad is separated from the edge of the recess by a space.

7. A device comprising:
a semiconductor substrate;
a first and a second image sensor at a front surface of the semiconductor substrate;
an interconnect structure on a front side of the semiconductor substrate, wherein the interconnect structure comprises a metal pad and a via connected to the metal pad;
an oxide layer over and contacting a back surface of the semiconductor substrate, wherein the oxide layer is on a backside of the semiconductor substrate;
a polysilicon layer over the oxide layer, wherein the polysilicon layer comprises a p-type impurity;
a metal shielding layer over the polysilicon layer, wherein the metal shielding layer is over and aligned to the first image sensor; and
a passivation layer over the metal shielding layer;
a recess penetrating through the semiconductor substrate, wherein the polysilicon layer extends to an edge of the recess; and
an electrical pad having a portion in the recess, wherein the electrical pad contacts the metal pad.

8. The device of claim 7 , wherein the p-type impurity is distributed to substantially an entirety of the polysilicon layer.

9. The device of claim 7 , wherein the p-type impurity is distributed to a middle layer of the polysilicon layer, and wherein an upper layer and a bottom layer of the polysilicon layer are substantially free from p-type impurities, and wherein the upper layer and a bottom layer are overlying and underlying the middle layer, respectively.

10. The device of claim 7 further comprising a dielectric layer between the metal shielding layer and the polysilicon layer, wherein the dielectric layer and the metal shielding layer have edges aligned with each other.

11. The device of claim 7 , wherein the oxide layer comprises an oxide of the material of the semiconductor substrate, and wherein the oxide layer is in physical contact with the back surface of the semiconductor substrate.

12. The device of claim 7 , wherein the metal shielding layer comprises aluminum copper.

13. The device of claim 7 , wherein the electrical pad is separated from the edge of the recess by a space.

14. A device comprising:
a semiconductor substrate comprising a front side and a backside;
a metal pad on the front side of the semiconductor substrate;
a polysilicon layer on the backside of the semiconductor substrate, wherein the polysilicon layer comprises a p-type impurity, with a middle portion having a gradient p-type impurity distribution, and having a highest p-type impurity concentration, and an upper portion higher than the middle portion and a lower portion lower than the middle portion, with the upper portion and the lower portion having p-type impurity concentrations lower than an impurity concentration of the middle portion;
a dielectric layer on the backside of the semiconductor substrate, wherein the dielectric layer is between the semiconductor substrate and the polysilicon layer;
a recess extending from a back surface of the semiconductor substrate to penetrate through the semiconductor substrate, wherein both the polysilicon layer and the dielectric layer extend to an edge of the recess; and
an electrical pad having a portion in the recess, wherein the electrical pad contacts the metal pad.

15. The device of claim 14 further comprising:
a passivation layer contacting a sidewall of the polysilicon layer, wherein the passivation layer comprises a dielectric material, and penetrates through the semiconductor substrate.

16. The device of claim 14 further comprising:
an image sensor in the semiconductor substrate; and
a metal shielding layer over the polysilicon layer, wherein the metal shielding layer is over and aligned to the image sensor.

17. The device of claim 16 further comprising an additional dielectric layer over and contacting the polysilicon layer, wherein the additional dielectric layer extends beyond opposite sidewalls of the metal shielding layer.

18. The device of claim 14 , wherein the electrical pad is separated from the edge of the recess by a space.

Assignees

• Jangjian Shiu-Ko
• Chen Kei-Wei
• Wang Ying-Lang
• Taiwan Semiconductor Mfg

Inventors

• Jangjian Shiu-Ko
• Chen Kei-Wei
• Wang Ying-Lang

Classifications

• H10F39/199

  Back-illuminated image sensors · CPC title

• H10F39/024

  of coatings or optical elements · CPC title

• H10F39/8057 Primary

  Optical shielding · CPC title

• H01L27/14623 Primary

  Electricity · mapped topic

• H01L27/14685

  Electricity · mapped topic