Substrate warpage control using external frame stiffener

Patent metadata

Field	Value
Publication number	US-9355966-B2
Application number	US-201313937040-A
Country	US
Kind code	B2
Filing date	Jul 8, 2013
Priority date	Jul 8, 2013
Publication date	May 31, 2016
Grant date	May 31, 2016

Abstract

A chip package and methods of manufacturing the same are disclosed. In particular, a chip package comprising a ball grid array is disclosed in which the chip package includes a package substrate supporting the ball grid array and in which the chip package further includes a warpage control frame that helps to minimize or mitigate warpage of the chip package.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a substrate having a first major surface and an opposing second major surface;
a semiconductor chip connected to the first major surface of the substrate via a plurality of electrically-conductive bumps;
a lid connected to the first major surface of the substrate, wherein a connection between the lid and the first major surface of the substrate at least partially surrounds the chip and the plurality of electrically-conductive bumps, wherein the connection between the lid and the first major surface of the substrate is established at least at a perimeter of the first major surface of the substrate;
a ball grid array established on the second major surface of the substrate; and
a warpage control frame configured to control a warpage of the semiconductor package comprising:
a perimeter section having a perimeter configured to match a perimeter of the substrate and the lid of the semiconductor package, the perimeter section further defining an internal void volume of the warpage control frame, wherein the perimeter section is configured to substantially surround the ball grid array such that a plurality of balls in the ball grid array structure are disposed within the internal void volume of the warpage control frame, the perimeter section comprising a thickness that is between 10% and 75% a height of the ball grid array structure;
a first cross member that travels through the internal void volume separating the internal void volume into first and second internal void volumes such that the ball grid array structure is separated into a first plurality of balls disposed within the first internal void volume and a second plurality of balls disposed within the second internal void volume; and
a second cross member that also travels through the internal void volume and intersects the first cross member such that the second cross member travels through the first and second internal void volumes further separating the first and second internal void volumes into smaller void volumes, wherein a divided plurality of balls in the ball grid array structure are disposed in each of the smaller void volumes.

2. The semiconductor package of claim 1 , wherein the perimeter section of the warpage control frame is continuous and completely surrounds the ball grid array.

3. The semiconductor package of claim 2 , wherein the perimeter section of the warpage control frame is connected to the second major surface via an adhesive at connection locations along the perimeter of the second major surface.

4. The semiconductor package of claim 3 , wherein the lid completely surrounds the chip and is attached to the substrate at locations substantially opposite to the connection locations of the connected perimeter section of the warpage control frame.

5. The semiconductor package of claim 4 , wherein the lid hermetically seals the chip, wherein the lid comprises at least one of copper, tin, steel, aluminum, silver, and gold, and wherein the lid is in thermal communication with the chip via a thermal interface such that heat produced in the chip is allowed to travel to the lid via the thermal interface.

6. The semiconductor package of claim 1 wherein the thickness of the warpage control frame is between 0.2 mm and 0.4 mm.

7. The semiconductor package of claim 1 , wherein a width of the perimeter section is less than 1.0 mm.

8. The semiconductor package of claim 1 , wherein the first cross member is connected to the perimeter section at two discrete points.

9. The semiconductor package of claim 8 , wherein the first cross member has a thickness less than the thickness of the perimeter section.

10. The semiconductor package of claim 1 , wherein the lid is configured to dissipate heat provided by the semiconductor chip to the substrate at least at the connection between the lid and the first major surface, wherein the lid has a first coefficient of thermal expansion (CTE), wherein the substrate has a different second CTE, and wherein the mechanical displacement of the substrate is caused by a mismatch between the first CTE and the second CTE.

11. A chip package, comprising:
a semiconductor die;
a substrate on which the semiconductor die is mounted;
a lid that substantially seals the semiconductor die within a cavity established about the substrate, wherein the lid is attached to the substrate at least at a perimeter of the substrate;
a ball grid array established on the substrate in opposition to the semiconductor die and the lid; and
a warpage control frame connected to the substrate at least at the perimeter of the substrate and configured to prevent warpage of the substrate by providing mechanical reinforcement to the substrate on a side of the substrate opposite the attached lid, the warpage control frame comprising:
a perimeter section having a perimeter configured to match the perimeter of the substrate and the lid of the chip package, the perimeter section further defining an internal void volume of the warpage control frame, wherein the perimeter section is configured to substantially surround the ball grid array such that a plurality of balls in the ball grid array structure are disposed within the internal void volume of the warpage control frame, the perimeter section comprising a thickness that is between 10% and 75% a height of the ball grid array structure;
a first cross member that travels through the internal void volume separating the internal void volume into first and second internal void volumes such that the ball grid array structure is separated into a first plurality of balls disposed within the first internal void volume and a second plurality of balls disposed within the second internal void volume; and
a second cross member that also travels through the internal void volume and intersects the first cross member such that the second cross member travels through the first and second internal void volumes further separating the first and second internal void volumes into smaller void volumes, wherein a divided plurality of balls in the ball grid array structure are disposed in each of the smaller void volumes.

12. The package of claim 11 , wherein the warpage control frame is established on the substrate such that it completely surrounds the ball grid array.

13. The package of claim 12 , wherein the perimeter section of the warpage control frame is connected to the substrate via an adhesive at connection locations along the perimeter of the substrate.

14. The package of claim 11 , wherein the warpage control frame is mounted to the substrate at mount locations substantially opposite to attachment locations of the attached lid.

15. The package of claim 14 , wherein the lid comprises an elevated portion that is in contact with the semiconductor die via a thermal interface as well as a connection portion that is attached to the substrate via an adhesive, wherein the connection portion substantially surrounds the semiconductor die and wherein the connection portion directly opposes the lid where it attaches to the substrate.

16. The package of claim 15 , wherein a width of the warpage control frame is less than a width of the adhesive that attaches the lid to the substrate.

17. The package of claim 11 , wherein the warpage control frame comprises a stamped metal.

18. A warpage control frame adapted for use in controlling warpage of a chip package having a ball grid array structure, the warpage control frame comprising:
a perimeter section having a perimeter configured to match a perimeter of a substrate and

Assignees

• Avago Technologies General Ip

Inventors

• Gallegos Adam
• Dauksher Walter J

Classifications

• H10W76/17

  characterised by their materials · CPC title

• H10W76/67

  characterised by their materials · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W72/877

  Bump connectors and die-attach connectors · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title