Semiconductor device

Patent metadata

Field	Value
Publication number	US-9355937-B2
Application number	US-201414465884-A
Country	US
Kind code	B2
Filing date	Aug 22, 2014
Priority date	Nov 29, 2013
Publication date	May 31, 2016
Grant date	May 31, 2016

Abstract

A semiconductor device includes a semiconductor substrate, a first metal layer, a barrier metal layer, and a second metal layer. The semiconductor substrate includes a front surface and a back surface. A semiconductor element and an electrode of the semiconductor element are located on the front surface. An opening in the back surface reaches a lower surface of the electrode, and the opening is defined by a side surface and a bottom surface. The first metal layer covers the side surface and the bottom surface. The barrier metal layer covers the first metal layer in the opening. The second metal layer is in contact with solder in the opening and is closer to the electrode than parts of the barrier metal layer. The second metal layer is laminated on the barrier metal layer and covers at least a part of the barrier metal layer in the opening.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor substrate including a front surface and a back surface;
a semiconductor element and an electrode of the semiconductor element located on the front surface of the semiconductor substrate;
an opening on the back surface of the semiconductor substrate and reaching a lower surface of the electrode, wherein
the opening is defined by a side surface and a bottom surface,
the bottom surface is located at the lower surface of the electrode, and
the back surface of the semiconductor substrate and the side surface of the opening join at an edge of the opening;

a first metal layer covering the side surface of the opening and the bottom surface of the opening;
a barrier metal layer covering the first metal layer in the opening;
a second metal layer including a first part inside the opening, covering the barrier metal layer, and located directly opposite the bottom surface of the opening, and a second part outside the opening and covering part of the barrier metal layer at the edge of the opening, opposite the back surface of the semiconductor substrate, wherein the first part of the second metal layer is not in contact with the second part of the second metal layer, and
solder filling the opening and in contact with the first part of the second metal layer.

2. The semiconductor device according to claim 1 , wherein the second metal layer does not cover at least a portion of the barrier metal layer on the side surface of the opening.

3. The semiconductor device according to claim 1 , wherein the barrier metal layer is selected from the group consisting of nickel, platinum, lead, titanium, and cobalt.

4. The semiconductor device according to claim 1 , wherein the barrier metal layer is an oxide layer of a material selected from the group consisting of nickel, platinum, lead, titanium, and cobalt.

5. The semiconductor device according to claim 1 , wherein
the barrier metal layer includes:
a first barrier metal layer, and
a second barrier metal layer,

the first barrier metal layer and the second barrier metal layer are laminated on each other at least once,
the second barrier metal layer has a lower stress than the first barrier metal layer.

6. The semiconductor device according to claim 5 , wherein
the first barrier metal layer is nickel, and
the second barrier metal layer is a material selected from the group consisting of platinum, lead, titanium, gold, aluminum, niobium, and copper.

7. The semiconductor device according to claim 5 , wherein the first barrier metal layer is thicker than the second barrier metal layer.

8. The semiconductor device according to claim 1 , wherein the barrier metal layer extends beyond the edge of the opening and onto the back surface of the semiconductor substrate, from inside the opening, at a periphery of the opening.

9. The semiconductor device according to claim 1 , wherein
the semiconductor element is a transistor including a gate, a source, and a drain located on the front surface of the substrate, and
the electrode is a source electrode located on the source.

10. The semiconductor device according to claim 1 , wherein
the first metal layer and the second metal layer include gold, and
the barrier metal layer includes nickel.

11. The semiconductor device according to claim 1 , wherein the side surface of the opening is substantially perpendicular to the back surface of the substrate.

Assignees

• Mitsubishi Electric Corp

Inventors

• Koyama Hidetoshi

Classifications

• H10W72/01953

  by etching · CPC title

• H10W72/01938

  in gaseous form, e.g. by CVD or PVD · CPC title

• H10W72/01935

  by plating, e.g. electroless plating or electroplating · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/942

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title