Cooling channels in 3DIC stacks

Patent metadata

Field	Value
Publication number	US-9355933-B2
Application number	US-201314132515-A
Country	US
Kind code	B2
Filing date	Dec 18, 2013
Priority date	Nov 13, 2008
Publication date	May 31, 2016
Grant date	May 31, 2016

Abstract

An integrated circuit structure includes a die including a semiconductor substrate; dielectric layers over the semiconductor substrate; an interconnect structure including metal lines and vias in the dielectric layers; a plurality of channels extending from inside the semiconductor substrate to inside the dielectric layers; and a dielectric film over the interconnect structure and sealing portions of the plurality of channels. The plurality of channels is configured to allow a fluid to flow through.

First claim

What is claimed is:

1. A method comprising:
forming a wafer comprising:
forming a first interconnect structure comprising metal lines and vias in first dielectric layers, wherein the first interconnect structure is on a front side of a first semiconductor substrate;
forming a first plurality of channels with at least a portion in the first dielectric layers; and
laminating a dielectric film over the first interconnect structure and sealing portions of the first plurality of channels, wherein the portions of the first plurality of channels are configured to allow a fluid flowing through.

2. The method of claim 1 , wherein the step of forming the first plurality of channels comprises:
forming through-substrate vias (TSVs) in the first semiconductor substrate;
after the step of forming the first interconnect structure, etching the first dielectric layers to form the first plurality of channels in the first interconnect structure; and
removing the TSVs to extend the first plurality of channels into the first semiconductor substrate.

3. The method of claim 2 , wherein the step of removing the TSVs is performed after the step of laminating the dielectric film.

4. The method of claim 1 , wherein the first plurality of channels comprises:
a first portion routing in a first layer of the first dielectric layers and not in a second layer of the first dielectric layers; and
a second portion routing in the second layer and not in the first layer, wherein the first portion and the second portion are vertically misaligned.

5. The method of claim 1 , wherein the forming the first plurality of channels comprises:
during the step of forming the first interconnect structure, forming metal lines and vias in a form of interconnected metal pipes, with materials of the first dielectric layers filling the metal pipes; and
removing the materials of the first dielectric layers in the metal pipes.

6. The method of claim 1 further comprising bonding a second die to a first die in the wafer.

7. The method of claim 6 , wherein the second die comprises:
a second semiconductor substrate;
a second interconnect structure comprising metals and vias in second dielectric layers and on a front side of the second semiconductor substrate; and
a second plurality of channels in the second dielectric layers, wherein after the step of bonding the second die to the first die, the first plurality of channels and the second plurality of channels are interconnected.

8. The method of claim 6 , wherein the second die comprises no channel connected to the first plurality of channels.

9. The method of claim 1 further comprising attaching a first fluidic tube and a second fluidic tube to an inlet and an outlet of the first plurality of channels, respectively.

10. The method of claim 9 further comprising conducting a cooling agent into the first fluidic tube, wherein the cooling agent flows through the first plurality of channels to the second fluidic tube.

11. A method comprising:
forming a wafer comprising:
providing a first semiconductor substrate;
forming a plurality of through-substrate vias (TSVs) in the first semiconductor substrate;
forming a first interconnect structure comprising metal lines and vias in first dielectric layers and on a front side of the first semiconductor substrate, wherein the metal lines and vias form interconnected metal pipes encircling portions of the first dielectric layers;
removing the portions of the first dielectric layers encircled by the interconnected metal pipes to form a first plurality of channels in the first dielectric layers;
laminating a dielectric film on the first interconnect structure and sealing the first plurality of channels;
polishing a backside of the first semiconductor substrate to expose the plurality of TSVs; and
removing the plurality of TSVs to extend the first plurality of channels into the first semiconductor substrate.

12. The method of claim 11 further comprising attaching a first fluidic tube and a second fluidic tube to a first one and a second one of the first plurality of channels left by the removed TSVs.

13. The method of claim 11 , wherein the step of removing the TSVs is performed after the step of laminating the dielectric film.

14. The method of claim 11 , wherein the first plurality of channels comprises:
a first portion routing in a first layer of the first dielectric layers and not in a second layer of the first dielectric layers; and
a second portion routing in the second layer and not in the first layer, wherein the first portion and the second portion are not vertically overlapped.

15. The method of claim 11 further comprising bonding a second die to a first die in the wafer.

16. The method of claim 15 , wherein the second die comprises:
a second semiconductor substrate;
a second interconnect structure comprising metal lines and vias in second dielectric layers and on a front side of the second semiconductor substrate; and
a second plurality of channels in the second dielectric layers, wherein after the step of bonding the second die to the first die, the first plurality of channels and the second plurality of channels are interconnected.

17. The method of claim 11 further comprising attaching a first fluidic tube to a first opening left by a first one of the removed TSVs and a second opening left by a second one of the removed TSVs.

18. A method comprising:
forming a through-substrate via (TSV) extending into a semiconductor substrate;
forming an interconnect structure comprising dielectric layers and metal features in the dielectric layers, wherein the interconnect structure is on a front side of the semiconductor substrate, and the metal features form interconnected metal pipes encircling a region of the interconnect structure;
etching portions of the dielectric layers in the region to form a first channel in the dielectric layers;
sealing the first channel with a film, wherein the film and the TSV are on opposite sides of the interconnect structure;
polishing a backside of the semiconductor substrate to expose the TSV;
etching the TSV to form a second channel in the semiconductor substrate; and
etching a metal feature exposed to the second channel to interconnect the first channel and the second channel as a continuous channel.

19. The method of claim 18 further comprising attaching a fluidic tube to the second channel.

20. The method of claim 18 , wherein the semiconductor substrate is comprised in a first die, and the method further comprises bonding a second die to the first die.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Ching Kai-Ming
• Hsiao Ching-Wen
• Wang Tsung-Ding
• Tseng Ming Hung
• Chen Chen-Shien

Classifications

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W72/944

  Dispositions of multiple bond pads · CPC title

• H10W72/942

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title