Package-on-package devices and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9355931-B2
Application number	US-201414516764-A
Country	US
Kind code	B2
Filing date	Oct 17, 2014
Priority date	Jan 23, 2014
Publication date	May 31, 2016
Grant date	May 31, 2016

Abstract

Package-on-package (POP) devices and methods of manufacturing the POP devices are provided. In the POP devices, a thermal interface material layer disposed between lower and upper semiconductor packages may contact about 70% or greater of an area of a top surface of a lower semiconductor chip. According to methods, the upper semiconductor package may be mounted on the lower semiconductor chip using a weight.

First claim

What is claimed is:

1. A method of manufacturing a package-on-package (POP) device, the method comprising:
applying a thermal interface material composition on a lower semiconductor package including a lower semiconductor chip and a lower package substrate, wherein the thermal interface material composition has a thermal conductivity and comprises a resin layer and filler particles comprising a metal that are dispersed in the resin layer;
placing an upper semiconductor package on the lower semiconductor package; and
pressing the upper semiconductor package toward the lower semiconductor package to press the thermal interface material composition,
wherein pressing the upper semiconductor package comprises putting a weight on the upper semiconductor package to press the upper semiconductor package toward the lower semiconductor package by a mass of the weight such that the thermal interface material composition is pressed,
wherein putting the weight on the upper semiconductor package comprises placing the lower and the upper semiconductor packages in a guide comprising a vertical portion that is proximate to and aligned with sidewalls of the lower and upper semiconductor packages and a horizontal portion that is over and substantially parallel to the upper semiconductor package,
wherein the horizontal portion of the guide comprises a hole at a central portion thereof, and
wherein the weight comprises a protruding portion that extends through the hole of the guide.

2. The method of claim 1 , wherein the mass of the weight is in a range of about 5 g to about 50 g.

3. The method of claim 1 , wherein the weight is put on the upper semiconductor package so as to cover an entire portion of the lower semiconductor chip.

4. The method of claim 1 , further comprising:
heating the thermal interface material composition to form a thermal interface material layer while pressing the upper semiconductor package.

5. The method of claim 4 , wherein the thermal interface material composition is pressed to contact about 70% or greater of an area of a top surface of the lower semiconductor chip.

6. A method of manufacturing a package-on-package (POP) device, the method comprising:
providing a lower semiconductor package including a lower package substrate, a lower semiconductor chip mounted on the lower package substrate, and a lower solder ball that is bonded to a top surface of the lower package substrate and spaced apart from the lower semiconductor chip;
providing a thermal interface material composition on the lower semiconductor package, wherein the thermal interface material composition has a thermal conductivity and comprises a resin layer and filler particles comprising a metal that are dispersed in the resin layer;
providing an upper semiconductor package on the lower semiconductor package, the upper semiconductor package including an upper package substrate, an upper semiconductor chip mounted on the upper package substrate, and an upper solder ball bonded to a bottom surface of the upper package substrate, wherein the thermal interface material composition is between the lower semiconductor package and the upper semiconductor package; and
pressing the upper semiconductor package toward the lower semiconductor package,
wherein pressing the upper semiconductor package comprises putting a weight on the upper semiconductor package to press the upper semiconductor package toward the lower semiconductor package by a mass of the weight such that the thermal interface material composition is pressed,
wherein putting the weight on the upper semiconductor package comprises placing the lower and the upper semiconductor packages in a guide comprising a vertical portion that is proximate to and aligned with sidewalls of the lower and upper semiconductor packages and a horizontal portion that is over and substantially parallel to the upper semiconductor package;
wherein the horizontal portion of the guide comprises a hole at a central portion thereof, and
wherein the weight comprises a protruding portion that extends through the hole of the guide.

7. The method of claim 6 , wherein:
the lower semiconductor package further comprises a mold layer that covers a sidewall of the lower semiconductor chip and the lower package substrate and includes a hole exposing the lower solder ball; and
providing the upper semiconductor package on the lower semiconductor package comprises inserting the upper solder ball into the hole.

8. The method of claim 6 , wherein the weight is put on the upper semiconductor package so as to cover an entire portion of the lower semiconductor chip.

9. The method of claim 6 , further comprising:
heating the thermal interface material composition to form a thermal interface material layer and heating the lower solder ball and the upper solder ball to form a connection solder ball connecting the lower semiconductor package and the upper semiconductor package while pressing the upper semiconductor package.

10. The method of claim 9 , wherein the thermal interface material composition is pressed to contact about 70% or greater of an area of a top surface of the lower semiconductor chip.

11. A method of manufacturing a package-on-package (POP) device, the method comprising:
providing a lower semiconductor package including a lower package substrate, a lower semiconductor chip mounted on the lower package substrate, and a lower solder ball that is bonded to a top surface of the lower package substrate and spaced apart from the lower semiconductor chip;
applying a thermal interface material composition on the lower semiconductor chip, wherein the thermal interface material composition has a thermal conductivity and comprises a resin layer and filler particles comprising a metal that are dispersed in the resin layer;
providing an upper semiconductor package on the lower semiconductor package and the thermal interface material composition, the upper semiconductor package including an upper package substrate, an upper semiconductor chip mounted on the upper package substrate, and an upper solder ball bonded to a bottom surface of the upper package substrate; and
pressing and heating the thermal interface material composition to widen a contact area between the thermal interface material composition and the lower semiconductor chip and pressing and heating the lower and the upper solder balls to melt the lower and the upper solder balls such that the lower and upper solder balls are bonded to each other, wherein the thermal interface material composition is between the lower semiconductor package and the upper semiconductor package,
wherein pressing and heating the thermal interface material composition comprises putting a weight on the upper semiconductor package to press the upper semiconductor package toward the lower semiconductor package by a mass of the weight such that the thermal interface material composition is pressed,
wherein putting the weight on the upper semiconductor package comprises placing the lower and the upper semiconductor packages in a guide comprising a vertical portion that is proximate to and aligned with sidewalls of the lower and upper semiconductor packages and a horizontal portion that is over and substantially parallel to the upper semiconductor package;
wherein the horizontal portion of the guide comprises a hole at a central portion thereof; and
wherein the weight comprises a protruding portion that extends through the hole of the guide.

12. The method of claim 11 , wherein:
pressing and heating the thermal interface material composition is performed to form a thermal interface material layer; and
pressing and heating the lower an

Assignees

• Kim Jongkook
• Lee Jangwoo
• Choi Kyoungsei
• Kang Sayoon
• Kim Donghan
• Shim Hwanggil
• Samsung Electronics Co Ltd

Inventors

• Kim Jongkook
• Lee Jangwoo
• Choi Kyoungsei
• Kang Sayoon
• Kim Donghan
• Shim Hwanggil

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/291

  characterised by containers, encapsulations, or other housings for the stacked chips · CPC title