Package on package (PoP) integrated device comprising a plurality of solder resist layers

Patent metadata

Field	Value
Publication number	US-9355898-B2
Application number	US-201414447399-A
Country	US
Kind code	B2
Filing date	Jul 30, 2014
Priority date	Jul 30, 2014
Publication date	May 31, 2016
Grant date	May 31, 2016

Abstract

Some features pertain to an integrated device that includes a first substrate, a first solder resist layer coupled to the first substrate, a second solder resist layer coupled to the first solder resist layer, and an opening in the first and second solder resist layers, the opening comprising a sidewall completely covered with the second solder resist layer, where a sidewall of the second solder resist layer covers a sidewall of the first solder resist layer. In some implementations, the opening is at least partially filled with an electrically conductive material. The electrically conductive material includes one of solder and/or an interconnect. The integrated device includes a first interconnect coupled to the electrically conductive material. The first interconnect is one of at least a solder, and/or an interconnect ball. In some implementations, the integrated device includes a pad coupled to the substrate, and a first interconnect coupled to the pad.

First claim

What is claimed is:

1. An integrated device comprising:
a first substrate;
a first solder resist layer coupled to the first substrate;
a second solder resist layer coupled to the first solder resist layer;
an opening in the first and second solder resist layers exposing a first sidewall of the first solder resist layer and a second sidewall of the second solder resist layer, wherein the second solder resist layer covers the first sidewall of the first solder resist layer;
an electrically conductive material aligned with the opening; and
a first interconnect distinct from the electrically conductive material and located within the electrically conductive material.

2. The integrated device of claim 1 , wherein the opening is at least partially filled with the electrically conductive material.

3. The integrated device of claim 2 , wherein the electrically conductive material includes solder.

4. The integrated device of claim 1 further comprising a second interconnect at least partially within the opening and coupled to the electrically conductive material.

5. The integrated device of claim 4 , wherein the second interconnect is a pillar.

6. The integrated device of claim 4 , wherein the second interconnect has a curved surface configured to receive at least a portion of the electrically conductive material containing the first interconnect.

7. The integrated device of claim 1 further comprising:
a pad coupled to the first substrate and to the electrically conductive material.

8. The integrated device of claim 1 , wherein the first interconnect is an interconnect ball.

9. The integrated device of claim 1 , further comprising a third solder resist layer between the first solder resist layer and the second solder resist layer.

10. The integrated device of claim 1 , wherein the integrated device is one of at least a package and/or package on package (POP) device.

11. The integrated device of claim 1 , wherein the integrated device is incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, and/or a laptop computer.

12. A method for fabricating an integrated device, comprising:
forming a first substrate;
forming a first solder resist layer on the first substrate;
forming a second solder resist layer on the first solder resist layer;
forming an opening in the first and second solder resist layers exposing a first sidewall of the first solder resist layer and a second sidewall of the second solder resist layer, wherein the second solder resist layer covers the first sidewall of the first solder resist layer;
forming an electrically conductive material aligned with the opening; and
forming a first interconnect distinct from the electrically conductive material and located within the electrically conductive material.

13. The method of claim 12 , wherein forming the electrically conductive material includes forming the electrically conductive material at least partially in the opening.

14. The method of claim 13 , wherein the electrically conductive material includes solder.

15. The method of claim 12 further comprising providing a second interconnect at least partially within the opening and coupled the electrically conductive material.

16. The method of claim 15 , wherein the second interconnect is a pillar.

17. The method of claim 15 , wherein forming the second interconnect further includes forming the second interconnect with a curved surface configured to receive at least a portion of the electrically conductive material containing the first interconnect.

18. The method of claim 12 further comprising:
forming a pad on the first substrate, wherein the pad is coupled to the electrically conductive material.

19. The method of claim 12 , wherein the first interconnect is an interconnect ball.

20. The method of claim 12 , further comprising forming a third solder resist layer between the first solder resist layer and the second solder resist layer.

21. The method of claim 12 , wherein the integrated device is one of at least a package and/or package on package (POP) device.

22. The method of claim 12 , wherein the integrated device is incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, and/or a laptop computer.

Assignees

• Qualcomm Inc

Inventors

• Kumar Rajneesh
• Jomaa Houssam Wafic
• Rae David Fraser
• Rouhana Layal
• Bchir Omar James

Classifications

• H10W70/687

  characterized by the outer layers being for protection, e.g. solder masks, or for protection against chemical or mechanical damage · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title