Method for fabrication of crack-free ceramic dielectric films

US9355761B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9355761-B2
Application numberUS-201414146357-A
CountryUS
Kind codeB2
Filing dateJan 2, 2014
Priority dateSep 30, 2011
Publication dateMay 31, 2016
Grant dateMay 31, 2016

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  1. Title

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  5. First independent claim

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  7. Citations and related patents

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Abstract

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The invention provides a process for forming crack-free dielectric films on a substrate. The process comprises the application of a dielectric precursor layer of a thickness from about 0.3 μm to about 1.0 μm to a substrate. The deposition is followed by low temperature heat pretreatment, prepyrolysis, pyrolysis and crystallization step for each layer. The deposition, heat pretreatment, prepyrolysis, pyrolysis and crystallization are repeated until the dielectric film forms an overall thickness of from about 1.5 μm to about 20.0 μm and providing a final crystallization treatment to form a thick dielectric film. The process provides a thick crack-free dielectric film on a substrate, the dielectric forming a dense thick crack-free dielectric having an overall dielectric thickness of from about 1.5 μm to about 20.0 μm.

First claim

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The invention claimed is: 1. A process for forming a crack-free dielectric comprising: providing a substrate; depositing a first dielectric precursor sol-gel layer having a thickness from about 0.3 μm to about 1.0 μm on the substrate; heating the first dielectric precursor sol-gel layer at a preheat temperature from about 100° C. to about 200° C. for a preheat temperature heating time from about 1 minute to about 30 minutes; initiating a three temperature step-wise preheat treatment comprising increasing the temperature from about 275° C. to about 325° C. in a pre-pyrolysis step and maintaining the temperature at the pre-pyrolysis temperature for a pre-pyrolysis period of time; increasing the temperature from about 375° C. to about 425° C. in a first pyrolysis step and maintaining the temperature at the first pyrolysis temperature for a first pyrolysis period of time; increasing the temperature from about 425° C. to about 475° C. in a second pyrolysis step and maintaining the temperature at a second pyrolysis temperature for a second pyrolysis period of time; initializing a crystallization treatment comprising increasing the temperature from about 600° C. to about 800° C. for a period of time to crystallize at least one layer wherein all heat treatments were performed in an ambient atmosphere and wherein temperature changes are achieved by moving the film into different zones; and repeating the deposition step, initial heating step, pyrolyzing and crystallization steps to form a dielectric precursor layer having a total thickness from about 1.5 μm to about 20.0 μm on the substrate. 2. The process of claim 1 further comprising heating the substrate and performing a final densification heating step by heating the substrate and the dielectric precursor to crystallize the dielectric precursor at a temperature from about 600° C. to about 800° C. for a final crystallization of time to form crystallized dielectric layer. 3. The process of claim 1 wherein the first dielectric precursor is selected from the group consisting of lanthanum doped lead zirconate titanate soluble gel solution (PLZT sol-gel) containing polyvinylpyrrolidone and a barium strontium titanate soluble gel solution (BST) containing polyvinylpyrrolidone. 4. The process of claim 3 wherein the PLZT is formed from 99% lead acetate tri-hydrate, 97% titanium isopropoxide, 70% zirconium n-propoxide in 1-propanol, 99.9% lanthanum acetate hydrate and PVP. 5. The process of claim 4 wherein the PLZT and PVP combination is aged for 12 hours and is passed through a 0.2-μm syringe filter. 6. The process of claim 5 wherein the filtered PLZT and PVP combination is deposited on a substrate comprising a platinized silicon wafer wherein said wafer includes a 100 nm thick Pt layer. 7. The process of claim 6 wherein the substrate is first preheated to 100° C. to 200° C. for 1 to 30 minutes in a furnace and second the substrate undergoes pyrolysis processes of rapid thermal annealing (RTA) and step-wise preheat treatment (SPT). 8. The process of claim 1 wherein the low temperature preheating time is from about 2 minutes to about 10 minutes. 9. The process of claim 1 wherein the deposition step, initial heating step, pyrolyzing and crystallization steps are repeated to form a dielectric precursor layer having a thickness from about 2.0 μm to about 5.0 μm on the substrate. 10. The process of claim 1 wherein the final crystallization time is from about 10 to about 40 minutes. 11. The process of claim 1 wherein said substrate comprises a base metal. 12. A process for forming a crack-free lanthanum doped lead zirconium titanate (PLZT) dielectric comprising: providing a substrate; depositing a first dielectric precursor PLZT sol-gel layer having a thickness from about 0.3 μm to about 1.0 μm on a substrate; heating the first dielectric precursor PLZT sol-gel layer at a preheat temperature from about 100° C. to about 200° C. for a preheat temperature heating time from about 1 minute to about 30 minutes; initiating a step-wise preheat treatment using three distinct temperatures comprising increasing the temperature from about 275° C. to about 325° C. in a pre-pyrolysis step and maintaining the temperature at the pre-pyrolysis temperature for a pre-pyrolysis period of time; increasing the temperature from about 375° C. to about 425° C. in a first pyrolysis step and maintaining the temperature at the first pyrolysis temperature for a first pyrolysis period of time; increasing the temperature from about 425° C. to about 475° C. in a second pyrolysis step and maintaining the temperature at the second pyrolysis temperature for a second pyrolysis period of time; initiating a crystallization treatment comprising increasing the temperature from about 600° C. to about 800° C. for a period of time to crystallize at least one layer; wherein all heat treatments were performed in an ambient atmosphere and wherein temperature changes are achieved by moving the film into different zones; and repeating the deposition step, initial heating step, pyrolyzing and crystallization steps to form a PLZT layer having a total thickness from about 1.5 μm to about 20.0 μm on a substrate to form a crystallized dielectric. 13. The process of claim 12 , further comprising heating the substrate and PLZT layer to crystallize the PLZT at a temperature from about 600° C. to about 800° C. for a final crystallization time to form crystallized PLZT. 14. The process of claim 12 wherein the pre-heating time is from about 2 minutes to about 10 minutes. 15. The process of claim 12 , wherein the first dielectric precursor is a lanthanum doped lead zirconium titanate (PLZT) soluble gel solution containing polyvinylpyrrolidone. 16. The process of claim 12 wherein said substrate comprises a base metal.

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Classifications

  • Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

  • the material having a perovskite structure, e.g. BaTiO3 · CPC title

  • the material containing two or more metal elements · CPC title

  • the material containing at least one rare earth metal element, e.g. oxides of lanthanides, scandium or yttrium · CPC title

  • the material containing zirconium, e.g. ZrO2 · CPC title

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What does patent US9355761B2 cover?
The invention provides a process for forming crack-free dielectric films on a substrate. The process comprises the application of a dielectric precursor layer of a thickness from about 0.3 μm to about 1.0 μm to a substrate. The deposition is followed by low temperature heat pretreatment, prepyrolysis, pyrolysis and crystallization step for each layer. The deposition, heat pretreatment, prepyrol…
Who is the assignee on this patent?
Uchicago Argonne Llc
What technology area does this patent fall under?
Primary CPC classification H01B19/04. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue May 31 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).