Device for offloading instructions and data from primary to secondary data path

Patent metadata

Field	Value
Publication number	US-9354893-B2
Application number	US-201213482630-A
Country	US
Kind code	B2
Filing date	May 29, 2012
Priority date	May 31, 2011
Publication date	May 31, 2016
Grant date	May 31, 2016

Abstract

Provided is an information processing device including an instruction cache, a data cache, first and second arithmetic unit groups including a plurality of arithmetic units capable of parallel operation, a first arithmetic-control circuit that generates one or more operation instructions for the first arithmetic unit group, and a second arithmetic-control circuit that generates one or more operation instructions for the second arithmetic unit group based on an instruction code of a fixed instruction register. The first arithmetic unit group sets the instruction code to the fixed instruction register according to an operation instruction generated based on a first specific instruction code by the first arithmetic-control circuit, and provides data to the second arithmetic unit group according to an operation instruction generated based on a second specific instruction code by the first arithmetic-control circuit. The second arithmetic unit group repeats operations based on the operation instructions by the second arithmetic-control circuit.

First claim

What is claimed is:

1. An information processing device comprising:
a first cache that stores a first instruction code comprising a plurality of specific instruction codes;
a second cache that stores data to be processed;
first and second arithmetic unit group circuits configured to execute operations on the data by a plurality of arithmetic units configured to operate in parallel;
a first arithmetic-control circuit configured to read the first instruction code, and to generate one or more operation instructions for the first arithmetic unit group circuit based on the first instruction code; and
a second arithmetic-control circuit configured to include a fixed instruction register fixed in length that stores a second instruction code, comprising one or more specific instruction codes, specified by the first arithmetic unit group circuit, and to generate one or more operation instructions for the second arithmetic unit group circuit based on the second instruction code, wherein
the first instruction code at least includes first and second specific instruction codes,
when the one or more operation instructions generated by the first arithmetic-control circuit include a first operation instruction on a basis of the first specific instruction code, the first arithmetic unit group circuit is configured to set the second instruction code to the fixed instruction register in accordance with the first operation instruction, and when the one or more operation instructions generated by the first arithmetic-control circuit include a second operation instruction on a basis of the second specific instruction code, the first arithmetic unit group circuit is configured to provide data to be processed by the second arithmetic unit group circuit to the second arithmetic unit group circuit, and
the second arithmetic unit group circuit repeatedly executes operations on a basis of the one or more operation instructions generated based on the second instruction code by the second arithmetic-control circuit,
wherein the first arithmetic unit group circuit and the second arithmetic unit group circuit have an identical but separate configuration of the plurality of arithmetic units, such that the first arithmetic unit group circuit and the second arithmetic unit group circuit have identical arithmetic units interconnected in the same manner.

2. The information processing device according to claim 1 , wherein the first instruction code includes a plurality of specific instruction codes executable by arithmetic units configured to operate in parallel in the first arithmetic unit group circuit.

3. The information processing device according to claim 1 , wherein the fixed instruction register stores a plurality of specific instruction codes executable by arithmetic units configured to operate in parallel in the second arithmetic unit group circuit.

4. The information processing device according to claim 1 , wherein, when the first arithmetic-control circuit indicates an operation based on an instruction code different from the first and second specific instruction codes, the first arithmetic unit group circuit is configured to perform the operation on the data in the second cache by an arithmetic unit in the first arithmetic unit group circuit.

5. The information processing device according to claim 1 , comprising:
an instruction cache that stores a third instruction code used in a first mode;
a data cache that stores data to be processed in the first mode;
a third arithmetic-control circuit configured to generate an operation instruction based on the third instruction code;
a first processor element that includes a first internal memory, which is one of the first cache or the second cache, which store the first instruction code and data to be processed, respectively, in a second mode, and the first arithmetic unit group circuit;
a second processor element that includes a second internal memory, which is another one of the first cache or the second cache, which store the first instruction code and data to be processed, respectively, in the second mode, and the second arithmetic unit group circuit;
a first switch that gives an operation indication from the third arithmetic-control circuit to the first processor element in the first mode and gives an operation indication from the first arithmetic-control circuit to the first processor element in the second mode; and
a second switch that gives an operation indication from the third arithmetic-control circuit to the second processor element in the first mode and gives an operation indication from the second arithmetic-control circuit to the second processor element in the second mode.

6. The information processing device according to claim 5 , wherein
the first internal memory stores data to be processed by the first arithmetic unit group circuit in the first mode, and stores one of the first instruction code and target data to be processed in the second mode,
the second internal memory stores data to be processed by the second arithmetic unit group circuit in the first mode, and stores another one of the first instruction code and the target data to be processed in the second mode, and
the first and second arithmetic unit group circuits are configured to execute operations on a basis of the operation indication from the third arithmetic-control circuit for data provided from the data cache in the first mode, and to perform reading and writing of the data in one of the first and second internal memories that is storing the target data to be processed in the second mode.

Assignees

• Kobayashi Yuki
• Nomoto Shohei
• Renesas Electronics Corp

Inventors

• Kobayashi Yuki
• Nomoto Shohei

Classifications

• G06F9/3891 Primary

  organised in groups of units sharing resources, e.g. clusters · CPC title

• G06F9/3893

  controlled in tandem, e.g. multiplier-accumulator · CPC title

• G06F9/3889

  controlled by multiple instructions, e.g. MIMD, decoupled access or execute · CPC title