Memory performance when speculation control is enabled, and instruction therefor
US-2015378915-A1 · Dec 31, 2015 · US
Systems and methods for handling instructions of in-order and out-of-order execution queues
US9110656B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9110656-B2 |
| Application number | US-201113210566-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 16, 2011 |
| Priority date | Aug 16, 2011 |
| Publication date | Aug 18, 2015 |
| Grant date | Aug 18, 2015 |
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Abstract
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A processor configured to provide instructions of a first instruction type to a first execution unit, and a second execution queue configured to provide instructions of a second instruction type to a second execution unit. A first instruction of the second instruction type is received. The first instruction is decoded by the decode/issue unit to determine operands of the first instruction. The operands of the first instruction are determined to include a dependency on a second instruction of the first instruction type stored in a first entry of the first execution queue. The first instruction is stored in a first entry of the second execution queue. A synchronization indicator corresponding to the first instruction in a second entry of the first execution queue is set immediately adjacent the first entry of the first execution queue, which indicates that the first instruction is stored in another execution queue.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of handling instructions in a processor comprising: receiving a first instruction of a second instruction type in the processor; decoding the first instruction by a decode/issue unit to determine operands of the first instruction; determining that the operands of the first instruction include a dependency on a second instruction of a first instruction type stored in a first entry of a first execution queue, wherein the first execution queue is c…
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Physics · mapped topic
- G06F9/30087Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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Frequently asked questions
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- What does patent US9110656B2 cover?
- A processor configured to provide instructions of a first instruction type to a first execution unit, and a second execution queue configured to provide instructions of a second instruction type to a second execution unit. A first instruction of the second instruction type is received. The first instruction is decoded by the decode/issue unit to determine operands of the first instruction. The …
- Who is the assignee on this patent?
- Tran Thang M, Nguyen Trinh Huy H, Freescale Semiconductor Inc
- What technology area does this patent fall under?
- Primary CPC classification G06F9/30087. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Aug 18 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).