System and method for reducing irregularities on the surface of a backside illuminated photodiode

Patent metadata

Field	Value
Publication number	US-9349902-B2
Application number	US-201213486833-A
Country	US
Kind code	B2
Filing date	Jun 1, 2012
Priority date	Jun 1, 2012
Publication date	May 24, 2016
Grant date	May 24, 2016

Abstract

System and method for processing a semiconductor device surface to reduce dark current and white pixel anomalies. An embodiment comprises a method applied to a semiconductor or photodiode device surface adjacent to a photosensitive region, and opposite a side having circuit structures for the device. A doped layer may optionally be created at a depth of less than about 10 nanometers below the surface of the substrate and may be doped with a boron concentration between about 1 E 13 and 1 E 16. An oxide may be created on the substrate using a temperature sufficient to reduce the surface roughness below a predetermined roughness threshold, and optionally at a temperature between about 300° C. and 500° C. and a thickness between about 1 nanometer and about 10 nanometers. A dielectric may then be created on the oxide, the dielectric having a refractive index greater than a predetermined refractive threshold, optionally at least about 2.0.

First claim

What is claimed is:

1. A method for processing a semiconductor comprising:
providing a semiconductor device having a substrate with a first surface, the first surface a result of a reduction of the substrate;
creating a doped layer in the substrate at about the first surface of the substrate;
performing a low temperature oxide deposition process, the low temperature oxide deposition process growing a first oxide on the first surface of the substrate and reducing a roughness of the first surface below a predetermined roughness threshold; and
creating a dielectric layer on a surface of the first oxide, the dielectric layer being continuous and having a uniform thickness, the dielectric layer contacting the first oxide and having a refractive index greater than a predetermined refractive threshold, and the dielectric layer having a multi-layered structure comprising a first layer and a second layer different from the first layer.

2. The method of claim 1 , wherein the semiconductor device has a photosensitive region in the substrate adjacent to the first surface and a circuit side opposite the first surface.

3. The method of claim 1 , wherein the first oxide is created at a temperature between about 300° C. and 500° C. and created to have a thickness between about 1 nanometer and about 10 nanometers.

4. The method of claim 1 , wherein the doped layer is a p-type layer doped with boron.

5. The method of claim 4 , wherein the doped layer has a dopant concentration between about 1 E 13 to about 1 E 16, and wherein the doped layer is less than about 10 nanometers deep.

6. The method of claim 4 , wherein the creating the p-type layer comprises implanting a dopant through the first surface of the substrate and performing a surface thermal anneal on the first surface of the substrate.

7. The method of claim 4 , wherein the p-type layer is epitaxially grown.

8. The method of claim 1 , wherein the dielectric layer comprises a material selected from the group consisting essentially of silicon nitride, silicon carbide and silicon dioxide.

9. The method of claim 1 , wherein the first layer is a silicon nitride layer and the second layer is a silicon dioxide layer, with the first layer overlying the second layer.

10. A method comprising:
providing a substrate having a photodiode formed at a circuit side of the substrate, the photodiode having a photosensitive region disposed in the substrate, the substrate further having a shallow trench isolation region (STI) extending from the circuit side of the substrate into the substrate;
reducing a thickness of the substrate by removing a portion of the substrate at a back side of the substrate opposite the circuit side while the photosensitive region is disposed in the substrate;
growing a low temperature oxide through a low temperature process on the back side of the substrate and at a first temperature to reduce a roughness of the back side below a predetermined roughness threshold;
forming a dielectric cap directly on the low temperature oxide at a second temperature greater than the first temperature, a material of the dielectric cap having a refractive index above a predetermined refractive index threshold, the dielectric cap contacting the low temperature oxide; and
forming a conducive feature over the dielectric cap, the conductive feature extending into the dielectric cap and the low temperature oxide.

11. The method of claim 10 , wherein the reducing the thickness of the substrate comprises removing a portion of the substrate that is disposed at the back side of the substrate and over the photosensitive region.

12. The method of claim 10 , wherein the predetermined roughness threshold is about 0.11 nanometers.

13. The method of claim 10 , wherein the material of the dielectric cap has a refractive index of at least about 2.0.

14. The method of claim 10 , wherein the dielectric cap has a thickness between about 100 nanometers and about 150 nanometers.

15. The method of claim 10 , wherein the low temperature oxide has a thickness between about 1 nanometer and about 10 nanometers.

16. A method comprising:
providing a substrate having photosensitive region adjacent to a first side and having a circuit side opposite the first side, wherein the first side of the substrate has a first roughness;
forming a p-type region at the first side of the substrate;
after the forming the p-type region, performing a low temperature oxide growth process to grow a low temperature oxide on the first side of the substrate, wherein the low temperature oxide growth process is performed at a first temperature sufficient to reduce the roughness of the first side to a second roughness that is below a predetermined roughness threshold and less than the first roughness;
forming a dielectric cap on the low temperature oxide at a second temperature greater than the first temperature, a material of the dielectric cap having a refractive index above a predetermined refractive index threshold, the dielectric cap having a substantially flat bottom surface in direct contact with the low temperature oxide;
forming a metal line directly on the dielectric cap, a portion of the metal line extends through the dielectric cap and the low temperature oxide; and
forming a passivation layer on the dielectric cap and over the metal line.

17. The method of claim 16 , wherein the low temperature oxide is formed at a temperature between about 300° C. and 500° C.

18. The method of claim 16 , wherein the roughness threshold is about 0.11 nanometers.

19. The method of claim 16 , wherein the portion of the metal line extends below an upper surface of the p-type region, with the upper surface extending away from the substrate.

20. The method of claim 16 , further comprising:
before the forming the passivation layer, forming a barrier layer on the metal line.

Assignees

• Jangjian Shiu-Ko
• Chen Kei-Wei
• Jeng Chi-Cherng
• Hong min hao
• Taiwan Semiconductor Mfg

Inventors

• Jangjian Shiu-Ko
• Chen Kei-Wei
• Jeng Chi-Cherng
• Hong min hao

Classifications

• H10D62/60

  Impurity distributions or concentrations · CPC title

• H10F71/00 Primary

  Manufacture or treatment of devices covered by this subclass (patterning processes to connect thin photovoltaic cells in integrated devices, or assemblies of multiple devices, having photovoltaic cells H10F19/33; manufacture or treatment of encapsulations or containers for integrated devices, or assemblies of multiple devices, having photovoltaic cells H10F19/80; manufacture or treatment of integrated devices, or assemblies of multiple devices, comprising at least one element in which radiation controls the flow of current H10F39/00) · CPC title

• H10F71/1215

  comprising at least two Group IV elements, e.g. SiGe · CPC title

• H10F30/2218

  the devices comprising active layers made of only Group IV-VI materials · CPC title

• H10F30/20

  the devices having potential barriers, e.g. phototransistors · CPC title