Release strategies for making transferable semiconductor structures, devices and device components

Patent metadata

Field	Value
Publication number	US-9349900-B2
Application number	US-201414246962-A
Country	US
Kind code	B2
Filing date	Apr 7, 2014
Priority date	Sep 20, 2006
Publication date	May 24, 2016
Grant date	May 24, 2016

Abstract

Provided are methods for making a device or device component by providing a multi layer structure having a plurality of functional layers and a plurality of release layers and releasing the functional layers from the multilayer structure by separating one or more of the release layers to generate a plurality of transferable structures. The transferable structures are printed onto a device substrate or device component supported by a device substrate. The methods and systems provide means for making high-quality and low-cost photovoltaic devices, transferable semiconductor structures, (opto-)electronic devices and device components.

First claim

We claim:

1. A method of making transferable semiconductor structures, said method comprising the steps of:
providing a multilayer structure comprising a plurality of functional layers and a plurality of release layers; wherein said release layers are positioned between functional layers in said multilayer structure, and at least one functional layer comprises a plurality of semiconductor structures anchored to said multilayer structure by a heterogeneous anchor, a homogeneous anchor, or a heterogeneous and a homogeneous anchor; and
releasing at least a portion of said semiconductor structures from said multilayer structure by separating one or more of said release layers from one or more of said functional layer and separating said plurality of semiconductor structures from said anchors, thereby generating said transferable semiconductor structures.

2. The method of claim 1 , wherein said plurality of semiconductor structures comprises a semiconductor device.

3. The method of claim 2 , wherein said semiconductor device is selected from the group consisting of: a P-N junction, a thin film transistor, a single junction solar cell, a multi-junction solar cell, a photodiode, a light emitting diode, a laser, a CMOS device, a MOSFET device, a MESFET device, and a HEMT device.

4. The method of claim 1 , wherein said semiconductor structures comprise a plurality of semiconductor thin films.

5. The method of claim 4 , wherein each of said semiconductor thin films is a single crystalline semiconductor layer.

6. The method of claim 4 , wherein each of said semiconductor thin films is selected from the group consisting of: an organic semiconductor layer, an inorganic semiconductor layer, a III-V semiconductor layer; and a group IV elemental or compound semiconductor.

7. The method of claim 4 , wherein said plurality of semiconductor thin films comprise at least two semiconductor thin films having different semiconductor materials or dopants.

8. The method of claim 1 , wherein said semiconductor structures comprise a doped semiconductor layer.

9. The method of claim 8 , wherein said doped semiconductor layer forms part of a P-N junction.

10. The method of claim 1 , wherein said semiconductor structures comprise a solar cell.

11. The method of claim 1 , wherein said semiconductor structures comprise material selected from the group consisting of:
Si, Ge, SiC, AlP, AlAs, AlSb, GaN, GaP, GaAs, GaSb, InP, InAs, GaSb, InP, InAs, InSb, ZnO, ZnSe, ZnTe, CdS, CdSe, ZnSe, ZnTe, CdS, CdSe, CdTe, HgS, PbS, PbSe, PbTe, AlGaAs, AlInAs, AlInP, GaAsP, GaInAs, GaInP, AlGaAsSb, AlGaInP, and GaInAsP.

12. The method of claim 1 , wherein said functional layer further comprises a dielectric layer, an electrode or conducting layer.

13. The method of claim 1 , wherein each plurality of semiconductor structures has a thickness selected from a range that is greater than 5 nm and less than 50,000 nm.

14. The method of claim 1 , wherein said multilayer structure has a functional layer number that is greater than or equal to 2 and less than or equal to 200, and a release layer number that is greater than or equal to 2 and less than or equal to 200.

15. The method of claim 1 further comprising the step of generating said multilayer structure on a substrate, wherein at least one release layer is provided between said functional layers and said substrate.

16. The method of claim 15 further comprising the step of repeating said steps of generating said multilayer structure on a substrate and releasing at least a portion of said semiconductor structures from said multilayer structure; wherein said substrate is reused during said step of repeating said steps of generating said multilayer structure on a substrate and releasing at least a portion of said semiconductor structures from said multilayer structure.

17. The method of claim 1 , wherein said plurality of semiconductor structures comprise:
III-V semiconductor epilayers, wherein at least two semiconductor epilayers have different semiconductor materials.

18. The method of claim 1 , wherein said plurality of semiconductor structures comprise:
a p-doped GaAs top layer;
a low-doped GaAs middle layer; and
an n-doped GaAs lower layer supported by said release layer.

19. The method of claim 17 , wherein said release layer comprises Al 0.9 Ga 0.1 As.

20. The method of claim 1 for making photovoltaics, wherein said semiconductor structures comprise:
a first layer of n-doped GaAs supported by said release layer;
a second layer supported by said first layer, said second layer comprising a back-surface field or Bragg-reflector layer;
a third layer comprising a n-doped GaAs base layer supported by said second layer;
a fourth layer comprising a p-doped GaAs emitter;
a fifth layer comprising a p-doped In 0.49 Ga 0.51 P passivation layer supported by said fourth layer; and
a sixth layer comprising a p-doped GaAs layer supported by said fifth layer.

21. The method of claim 20 , further comprising a buffer layer positioned between said first and second layer, wherein said buffer layer comprises n-doped GaAs.

22. The method of claim 20 , wherein said release layer comprises a layer of Al 0.96 Ga 0.04 As of sufficient thickness to avoid sagging of said multilayer.

23. The method of claim 22 , wherein said release layer thickness is greater than or equal to 300 nm and less than or equal to 2500 nm.

24. The method of claim 20 , wherein said plurality of functional layers are selected from a range that is greater than or equal to 2 and less than or equal to 200.

25. The method of claim 1 , further comprising providing said multilayer structure on a GaAs substrate.

26. The method of claim 25 , wherein each functional layer comprises an n-doped GaAs layer and a semi-insulating layer of AIGaAs.

27. The method of claim 26 , wherein said release layer is Al 0.96 Ga 0.04 As.

28. The method of claim 26 , wherein the number of said functional layers is greater than or equal to 2 and less than or equal to 200.

29. The method of claim 1 , wherein each functional layer comprises 15 stacked layers arranged from a top-most layer 1 to a bottom-most layer 15 supported by said release layer, and said stacked layers comprise:
1 GaAs:C
2 Al 0.45 Ga 0.55 As:C
3 Al 0.5 In 0.5 P:Mg
4 Al 0.25 Ga 0.25 In 0.5 P
5 Ga 0.44 In 0.56 P
6 Al 0.25 Ga 0.25 In 0.5 P
7 Ga 0.44 In 0.56 P
8 Al 0.25 Ga 0.25 In 0.5 P
9 Ga 0.44 In 0.56 P
12 Al 0.25 Ga 0.25 In 0.5 P
13 Al 0.5 I 0.5 P
14 Al 0.45 Ga 0.55 As:Te
15 GaAs:Te.

30. The method of claim 29 , wherein said release layer comprises Al 0.96 Ga 0.04 As and said multilayer structure is supported by a GaAs substrate.

31. A multi-layer stack system for providing transferable structures, said multi-layer stack system comprising:
a substrate;
a release layer that covers at least a portion of said substrate;
a plurality of functional layers supported by said release layer and said substrate, wherein adjacent functional layers are separated by a release layer positioned between adjacent functional layers;

wherein at least one of said functional layers comprises a plurality of semiconductor structures; and
wherein said semiconductor structures are connected to a heterogeneous anchor, a homogeneous anchor, or a heterogeneous anchor and a ho

Assignees

• Univ Illinois

Inventors

• Rogers John A
• Nuzzo Ralph G
• Meitl Matthew
• Ko Heung Cho
• Yoon Jongseung
• Menard Etienne
• Baca Alfred J

Classifications

• H10W72/0198

  batch processes · CPC title

• B82Y40/00

  Manufacture or treatment of nanostructures · CPC title

• B81C2201/0191

  Transfer of a layer from a carrier wafer to a device wafer · CPC title

• Y02E10/544

  Solar cells from Group III-V materials · CPC title

• Y02E10/547

  Monocrystalline silicon PV cells · CPC title