Method of manufacturing a TFT-LCD array substrate having light blocking layer on the surface treated semiconductor layer

Patent metadata

Field	Value
Publication number	US-9349760-B2
Application number	US-201514638478-A
Country	US
Kind code	B2
Filing date	Mar 4, 2015
Priority date	Jul 13, 2009
Publication date	May 24, 2016
Grant date	May 24, 2016

Abstract

A thin film transistor liquid crystal display (TFT-LCD) array substrate comprises a gate line, a data line, a pixel electrode and a thin film transistor. The pixel electrode and the thin film transistor are formed in a pixel region defined by intersecting of the gate line and the data line, and the thin film transistor comprises a gate electrode, a semiconductor layer, a source electrode and a drain electrode. Two separate parts of the surface of the semiconductor layer are treated by a surface treatment to form into an ohmic contact layer, and the source electrode and the drain electrode are connected with the semiconductor layer through the ohmic contact layer in the two separate parts, respectively.

First claim

What is claimed is:

1. A method of manufacturing a thin film transistor liquid crystal display (TFT-LCD) array substrate, comprising:
Step 1 of sequentially depositing a transparent conductive film and a gate metal film on a substrate, and patterning the transparent conductive film and the gate metal film to form a pixel electrode, a gate line and a gate electrode;
Step 2 of depositing a gate insulating layer and a semiconductor film on the substrate after the Step 1 and patterning the semiconductor film to form a semiconductor layer, wherein two separate parts of the surface of the semiconductor layer is treated by a surface treatment process to form into an ohmic contact layer; and
Step 3 of depositing a source/drain metal film on the substrate after the Step 2, and patterning the source/drain metal film to form a data line, a source electrode and a drain electrode by a patterning process, wherein the source electrode and the drain electrode respectively are connected with the semiconductor layer through the ohmic contact layer in the two separate parts;
wherein the Step 2 comprises:
sequentially depositing the gate insulating layer, the semiconductor film and a blocking film on the substrate after the Step 1;
applying a photoresist layer on the blocking film;
exposing the photoresist layer by a triple-tone mask to form a photoresist-completely-removed region, a photoresist-completely-retained region, a first photoresist-partially-retained region and a second photoresist-partially-retained region, wherein the photoresist-completely-removed region corresponds to the region of a first via hole, the photoresist-completely-retained region corresponds to the region of a blocking layer, the second photoresist-partially-retained region corresponds to the region of the semiconductor layer, and the first photoresist-partially-retained region corresponds to the region other than the above regions, and wherein after performing a developing process, the thickness of the photoresist in the photoresist-completely-retained region is not changed, the photoresist in the photoresist-completely-removed region is completely removed, the thickness of the photoresist in the first photoresist-partially-retained region and the second photoresist-partially-retained region is decreased, and the thickness of the photoresist in the second photoresist-partially-retained region is larger than that in the first photoresist-partially-retained region;
etching away the blocking film, the semiconductor film and the gate insulating layer in the photoresist-completely-removed region by a first etching process to form the first via hole;
completely removing the photoresist in the first photoresist-partially-retained region by a first ashing process to expose the blocking film in this region and retaining the photoresist in the second photoresist-partially-retained region and the photoresist-completely-retained region;
etching away the blocking film and the semiconductor film in the first photoresist-partially-retained region by a second etching process to form the semiconductor layer, wherein the semiconductor layer is positioned over the gate electrode;
completely removing the photoresist in the second photoresist-partially-retained region by a second ashing process to expose the blocking film in this region, and retaining the photoresist in the photoresist-completely-retained region;
etching away the blocking film in the second photoresist-partially-retained region by a third etching process to form the blocking layer, wherein the semiconductor layer is exposed on both sides of the blocking layer;
treating the exposed surface of the semiconductor layer by the surface treatment so that the surface of the semiconductor layer exposed on both sides of the blocking layer is formed into the ohmic contact layer, and
removing the remaining photoresist.

2. The method of claim 1 , wherein the Step 3 comprises:
depositing the source/drain metal film on the substrate after the Step 2, and
forming the data line, the source electrode and the drain electrode by a patterning process with a normal mask,
wherein one end of the source electrode is connected with the data line, and the other end thereof is connected with the semiconductor layer through the ohmic contact layer on one side of the blocking layer; one end of the drain electrode is connected with pixel electrode through the first via hole, and the other end thereof is connected with the semiconductor layer through the ohmic contact layer on the other side of the blocking layer; and a TFT channel region is formed between the source electrode and the drain electrode.

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Optoelectronics

Inventors

• Liu Xiang
• Xie Zhenyu
• Chen Xu

Classifications

• H10P76/20

  of masks comprising organic materials · CPC title

• H10P50/287

  by chemical means · CPC title

• H10P50/283

  by chemical means · CPC title

• H10D30/6739

  Conductor-insulator-semiconductor electrodes · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title