Semiconductor device with an isolation structure coupled to a cover of the semiconductor device

Patent metadata

Field	Value
Publication number	US-9349693-B2
Application number	US-201414451962-A
Country	US
Kind code	B2
Filing date	Aug 5, 2014
Priority date	Aug 5, 2014
Publication date	May 24, 2016
Grant date	May 24, 2016

Abstract

A system and method for packaging a semiconductor device that includes a structure to reduce electromagnetic coupling are presented. The semiconductor device is formed on a substrate. A cover is affixed to the substrate so as to extend over the semiconductor device. An isolation structure of electrically conductive material is coupled to the cover in between components of the semiconductor device, with the isolation structure being configured to reduce inductive coupling between those components during an operation of the semiconductor device. In one version, the isolation structure includes a first leg extending from a ground connection along a side wall of the cover to a cross member contiguous with a primary cover wall that extends over the semiconductor device between the components to be isolated electromagnetically.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate having a surface;
an electronic device formed on the substrate and comprising a first electrical component and a second electrical component;
a cover fabricated separate from and adhered to the substrate so as to extend over the first electrical component and the second electrical component, the cover including first and second side walls between which a primary wall extends; and
an isolation structure including:
a first cross member contiguous with the cover and extending over the surface of the substrate in between the first electrical component and the second electrical component, the first cross member being formed on the primary wall, and
a first leg located on the first side wall, wherein the first leg is electrically connected to the first cross member,

wherein the isolation structure is configured to reduce electromagnetic coupling between the first electrical component and the second electrical component during an operation of the electronic device.

2. The semiconductor device as recited in claim 1 , wherein the isolation structure is formed of electrically conductive material.

3. The semiconductor device as recited in claim 2 , wherein the electronic device has a ground potential node, and the isolation structure is electrically connected to the ground potential node.

4. The semiconductor device as recited in claim 3 , further comprising a capacitor coupling the isolation structure to the ground potential node.

5. The semiconductor device as recited in claim 2 , further comprising a first electrical connector projecting outward from the substrate and electrically connected directly to the isolation structure.

6. The semiconductor device as recited in claim 1 , wherein the isolation structure further comprises a second leg contiguous with the second side wall and electrically connected to both the first cross member and to a second electrical connector projecting outward from the substrate.

7. The semiconductor device as recited in claim 1 , wherein the isolation structure further comprises a second cross member mounted to the cover and electrically connected to the first electrical connector.

8. The semiconductor device as recited in claim 1 , wherein the isolation structure further comprises a second cross member mounted to the cover and electrically connected in common with the first cross member.

9. The semiconductor device as recited in claim 1 , further comprising first and second electrical connectors projecting from the substrate and parallel to two side walls of the cover, wherein the first cross member is electrically connected to the first and second electrical connectors.

10. The semiconductor device as recited in claim 9 , wherein the first cross member has a pair of apertures into which the first and second electrical connectors extend.

11. The semiconductor device as recited in claim 9 , wherein each of the first and second electrical connectors has a section configured to electrically connect to a printed circuit board on which the semiconductor device is mounted.

12. The semiconductor device as recited in claim 1 , wherein the isolation structure is mounted on one of an exterior surface and an interior surface of the cover.

13. The semiconductor device as recited in claim 1 , wherein the isolation structure is embedded inside the cover.

14. A method of fabricating a semiconductor device with isolation between components of the semiconductor device, the method comprising:
forming a first component on a substrate;
forming a second component on the substrate;
adhering a cover to the substrate, the cover including first and second side walls between which a primary wall extends; and
coupling an isolation structure of electrically conductive material to the cover by:
forming a cross member on the primary wall and in between the first and second component, and
locating a first leg on the first side wall, wherein the first leg is electrically connected to the cross member,

the isolation structure having at least a portion that is spaced from and extends over the substrate in between the first component and the second component, wherein the isolation structure being configured to reduce electromagnetic coupling between the first component and the second component during an operation of the semiconductor device.

15. The method as recited in claim 14 further comprising electrically connecting the first leg to an electrical node located on the substrate.

16. The method as recited in claim 14 , further comprising capacitively coupling the first leg to an electrical node located on the substrate.

17. The method as recited in claim 14 wherein coupling an isolation structure further comprises locating a second leg on the second side wall, wherein the second leg is electrically connected to the cross member.

18. The method as recited in claim 17 further comprising electrically connecting the first leg to an electrical node located on the substrate.

Assignees

• Lakshminarayan Viswanathan
• Watts Michael E
• Abdo David F
• Freescale Semiconductor Inc

Inventors

• Lakshminarayan Viswanathan
• Watts Michael E
• Abdo David F

Classifications

• H10W90/759

  between a chip and a laterally-adjacent discrete passive device · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/5475

  multiple bond wires connected to common bond pads at both ends of the wires · CPC title

• H10W72/5473

  multiple bond wires connected to a common bond pad · CPC title