Chip arrangement and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9349680-B2
Application number	US-201414147547-A
Country	US
Kind code	B2
Filing date	Jan 5, 2014
Priority date	Jan 5, 2014
Publication date	May 24, 2016
Grant date	May 24, 2016

Abstract

A chip arrangement is provided which comprises a carrier; and at least two chips arranged over the carrier; wherein a continuous insulating layer is arranged between the at least two chips and between the carrier and at least one of the at least two chips.

First claim

What is claimed is:

1. A chip arrangement comprising:
a carrier; and
at least two chips arranged over the carrier each chip comprising a top surface, a bottom surface and a lateral sidewall extending therebetween;
wherein a continuous insulating layer is arranged between the carrier and at least one of the at least two chips, and further vertically extends between the lateral sidewalls of the at least two chips.

2. The chip arrangement according to claim 1 , wherein the carrier comprises an electric conductive material.

3. The chip arrangement according to claim 1 , wherein the insulating layer comprises a material which has a melting temperature of above 200° C.

4. The chip arrangement according to claim 1 , wherein the insulating layer comprising at least one material out of the group consisting of:
a thermoset material,
a thermoplast material;
a rubber material; and
a mixture thereof.

5. The chip arrangement according to claim 1 ,
wherein the continuous insulating layer is a laminate layer.

6. The chip arrangement according to claim 1 , further comprising an encapsulation layer which is arranged over the at least two chips.

7. The chip arrangement according to claim 6 , further comprising interconnections extending through the encapsulation layer.

8. The chip arrangement according to claim 1 , wherein the continuous insulating layer is adapted to act as an adhesive material for the at least one of the at least two chips.

9. The chip arrangement according to claim 1 ,
wherein the carrier has a thickness in a range between 100 micrometer and 1,000 micrometer.

10. A chip arrangement comprising:
a carrier;
a first chip arranged on the carrier;
a second chip arranged on a continuous insulating layer and beside the first chip, wherein the continuous insulating layer is arranged over the first chip.

11. The chip arrangement according to claim 10 ,
wherein the continuous insulating layer is arranged on at least three sides of the first chip.

12. The chip arrangement according to claim 10 , further comprising an encapsulation layer.

13. Method of manufacturing a chip arrangement, the method comprising:
arranging a first chip on a carrier;
arranging a second chip on a continuous insulating layer; and
subsequently arranging the continuous insulating layer on the first chip arranged on the carrier;
wherein a plurality of second chips is arranged on the continuous insulating layer.

14. The method according to claim 13 ,
wherein the continuous insulating layer comprising a material which is adhesive when the second chip is arranged on the continuous insulating layer.

15. The method according to claim 13 , further comprising:
arranging an encapsulation layer on top of the second chip before the continuous insulating layer is arranged on the first chip arranged on the carrier.

16. The method according to claim 13 , further comprising:
arranging an encapsulation layer on top of the second chip during the arranging of the continuous insulating layer on the first chip arranged on the carrier.

17. The method according to claim 15 , further comprising opening of the encapsulation layer after it is arranged over the carrier.

18. The method according to claim 17 , wherein the opening of the encapsulation layer is performed by a laser.

19. The method according to claim 13 , further comprising a singularization step.

Assignees

• Infineon Technologies Austria

Inventors

• Mahler Joachim
• Strobel Peter
• Fuergut Edward

Classifications

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/10

  Configurations of laterally-adjacent chips · CPC title

• H10W74/121

  by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation · CPC title

• H10W74/014

  using batch processing · CPC title

• H10W72/9413

  on encapsulations · CPC title