Stackable semiconductor package and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9349611-B2
Application number	US-201313776567-A
Country	US
Kind code	B2
Filing date	Feb 25, 2013
Priority date	Mar 22, 2010
Publication date	May 24, 2016
Grant date	May 24, 2016

Abstract

A semiconductor package includes a set of stud bumps, which can be formed by wire bonding technology and can be bonded or joined to a semiconductor element to form a stacked package assembly. Since the process of bonding the semiconductor element to the stud bumps can be carried out without reflow, an undesirable deformation resulting from high temperatures can be controlled or reduced.

First claim

What is claimed is:

1. A manufacturing method, comprising:
providing a carrier;
disposing a semiconductor device over the carrier such that an active surface of the semiconductor device faces the carrier, wherein the semiconductor device includes a pad adjacent to the active surface;
forming a package body over the carrier and the semiconductor device, wherein the package body includes a first package surface and a second package surface opposite to the first package surface, and the first package surface faces the carrier;
forming a through-hole in the package body, wherein the through-hole extends between the first package surface and the second package surface;
separating the carrier from the package body;
forming a dielectric layer adjacent to the first package surface, wherein the dielectric layer exposes the pad and the through-hole;
forming a conductive via in the through-hole, wherein the conductive via includes a first end, adjacent to the first package surface, and a second end, adjacent to the second package surface;
forming a patterned conductive layer adjacent to the dielectric layer, wherein the patterned conductive layer is electrically connected to at least one of the pad and the first end of the conductive via; and
forming a stud bump adjacent to the second end of the conductive via.

2. The manufacturing method of claim 1 , wherein forming the stud bump is carried out using a wiring tool.

3. The manufacturing method of claim 1 , wherein the stud bump is one of a gold stud bump, an aluminum stud bump, and a copper stud bump.

4. The manufacturing method of claim 1 , wherein forming the conductive via and forming the patterned conductive layer are carried out substantially simultaneously.

5. The manufacturing method of claim 1 , wherein the patterned conductive layer is a first patterned conductive layer, and further comprising:
forming a second patterned conductive layer adjacent to the second package surface, wherein the second patterned conductive layer is electrically connected to the second end of the conductive via and the stud bump.

6. The manufacturing method of claim 5 , wherein forming the stud bump is such that the stud bump is laterally displaced from the conductive via.

7. The manufacturing method of claim 6 , wherein forming the stud bump is such that the stud bump is inwardly disposed with respect to the conductive via.

8. A manufacturing method, comprising:
providing a package structure including:
providing a package body comprising a semiconductor device including an active surface and a pad adjacent to the active surface, wherein the pad of the semiconductor device is exposed adjacent to a lower surface of the package body,
creating a through hole extending between the lower surface of the package body and an upper surface of the package body,
filling the through hole with a conductive via, and
forming an upper patterned conductive layer adjacent to the upper surface of the package body and electrically connected to an upper end of the conductive via; and

forming a stud bump over the upper patterned conductive layer, wherein the stud bump is laterally displaced from the conductive via.

9. The manufacturing method of claim 8 , wherein forming the stud bump is such that the stud bump includes a base portion and a protruded neck portion.

10. The manufacturing method of claim 8 , wherein forming the stud bump is such that the stud bump is inwardly disposed with respect to the conductive via.

11. The manufacturing method of claim 8 , wherein forming the stud bump is such that the stud bump is disposed outwardly of the side surface of the semiconductor device.

12. The manufacturing method of claim 8 , wherein providing the package structure is such that the package structure further includes a lower patterned conductive layer adjacent to the lower package surface and electrically connected to the pad of the semiconductor device and a lower end of the conductive via.

13. The manufacturing method of claim 8 , wherein the pad is a first pad, and further comprising:
providing a semiconductor element including a second pad; and
bonding the stud bump to the second pad to form a stacked package assembly.

14. The manufacturing method of claim 13 , wherein bonding the stud bump to the second pad is carried out by applying a temperature lower than a reflow temperature.

15. The manufacturing method of claim 8 , wherein the stud bump is a first stud bump, and further comprising:
providing a semiconductor element including a second stud bump; and
bonding the first stud bump to the second stud bump to form a stacked package assembly.

16. The manufacturing method of claim 15 , wherein bonding the first stud bump to the second stud bump is carried out by applying a temperature lower than a reflow temperature.

17. The manufacturing method of claim 15 , wherein bonding the first stud bump to the second stud bump is carried out by applying ultrasonic energy.

18. A manufacturing method, comprising:
providing a package structure including:
a semiconductor device including a pad,
a package body encapsulating the semiconductor device with the pad exposed adjacent to a lower surface of the package body,
a conductive structure at least partially extending between the lower surface of the package body and an upper surface of the package body,
an upper patterned conductive layer extending from an upper end of the conductive structure and along the upper surface of the package body, and
a lower patterned conductive layer extending from a lower end of the conductive structure and along the lower surface of the package body; and

forming a stacking element over the upper patterned conductive layer, wherein the stacking element includes a base portion and a protruded portion disposed over the base portion, and the stacking element is laterally displaced from the conductive structure.

19. The manufacturing method of claim 18 , wherein the stacking element is a stud bump.

20. The manufacturing method of claim 18 , wherein forming the stacking element is such that the stacking element is laterally disposed between the semiconductor device and the conductive structure.

Assignees

• Advanced Semiconductor Eng

Inventors

• Chen Chia-Ching
• Ding Yi-Chuan

Classifications

• H10W90/752

  between stacked chips · CPC title

• H10W90/725

  between a chip and a laterally-adjacent insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W74/473

  containing a filler · CPC title