Apparatus and method emulating a parallel interface to effect parallel data transfer from serial flash memory

Patent metadata

Field	Value
Publication number	US-9348783-B2
Application number	US-201313866128-A
Country	US
Kind code	B2
Filing date	Apr 19, 2013
Priority date	Apr 19, 2012
Publication date	May 24, 2016
Grant date	May 24, 2016

Abstract

Apparatus and method emulating a parallel interface to effect parallel data transfer from serial flash memory are provided. A field-programmable gate array (FPGA) may be coupled to a processor via a data bus. A serial flash memory may be coupled to the FPGA via a serial interface. The FPGA may be programmed to emulate a parallel interface by converting a serial data stream of boot code or operating software received from the serial flash memory to a parallel data stream to effect parallel data transfer over the data bus to the processor. The FPGA may be responsive to respective logic signals set by the processor to start access to the serial flash memory by pointing to at least one predefined location corresponding to at least one starting address of data to be transferred to the processor without using a plurality of address lines to access the serial flash memory.

First claim

The invention claimed is:

1. Apparatus comprising:
a processor;
a field-programmable gate array (FPGA) coupled to the processor by way of a data bus; and
a serial flash memory coupled to the FPGA by way of a serial interface,
wherein the FPGA is programmed to emulate a parallel interface by converting a serial data stream comprising boot code or operating software received from the serial flash memory to a parallel data stream to effect parallel data transfer over the data bus to the processor; and the FPGA to provide flow control to data being requested by the processor by monitoring a storage level of a data buffer coupled to receive the data being accessed from the serial flash memory.

2. The apparatus of claim 1 , wherein the serial flash memory comprises a NOR-based serial flash memory.

3. The apparatus of claim 1 , wherein the data bus comprises an external memory interface (EMIF) bus.

4. The apparatus of claim 1 , wherein the serial interface comprises a serial peripheral interface (SPI).

5. The apparatus of claim 4 , wherein the serial interface comprises a quad SPI.

6. The apparatus of claim 1 , wherein the FPGA is responsive to respective logic signals set by the processor to start access to the serial flash memory by pointing to at least one predefined location corresponding to at least one starting address of data to be transferred to the processor without using a plurality of address lines to access the serial flash memory.

7. The apparatus of claim 6 , wherein said least one predefined location is based on a type of data to be transferred.

8. The apparatus of claim 1 , wherein, when a number of words in the buffer is below a lower range threshold, the FPGA issues a plurality of wait commands to the data bus until the number of words in the data buffer refills to a predefined number of words.

9. The apparatus of claim 8 , wherein, when a number of words in the buffer is above an upper range threshold, the FPGA issues a plurality of halt commands until the number of words in the data buffer is reduced to a predefined number of words.

10. A circuit card assembly comprising the apparatus of claim 1 .

11. The circuit care assembly of claim 10 , wherein the FPGA is responsive to respective logic signals set by the processor to start access to the serial flash memory by pointing to at least one predefined location corresponding to at least one starting address of data to be transferred to the processor without using a plurality of address lines to access the serial flash memory.

12. Apparatus comprising:
a processor;
a field-programmable gate array (FPGA) coupled to the processor by way of a data bus; and
a serial flash memory coupled to the FPGA by way of a serial interface,
wherein the FPGA is programmed to emulate a parallel interface by converting a serial data stream comprising boot code or operating software received from the serial flash memory to a parallel data stream to effect parallel data transfer over the data bus to the processor,
wherein the FPGA is responsive to respective logic signals set by the processor to start access to the serial flash memory by pointing to at least one predefined location corresponding to at least one starting address of data to be transferred to the processor without using a plurality of address lines to access the serial flash memory.

13. A method comprising:
storing data representative of boot code in serial flash memory;
emulating by a field-programmable gate array (FPGA), coupled between the serial flash memory and a processor, a parallel interface by converting a serial data stream comprising the data representative of the boot code received from the serial flash memory to a parallel data stream to effect parallel data transfer over a data bus to the processor; and
booting the processor with the data representative of the boot code by using respective logic signals set by the processor to start access to the serial flash memory by pointing to at least one predefined location corresponding to at least one starting address of the data representative of the boot code to be transferred to the processor via the FPGA without using a plurality of address lines to access the serial flash memory.

14. The method of claim 13 , wherein the serial flash memory comprises a NOR-based serial flash memory.

15. The method of claim 13 , wherein the data bus comprises an external memory interface (EMIF) bus.

16. The method of claim 13 , wherein the FPGA is coupled to the serial flash memory by a quad serial interface.

17. The method of claim 13 , further comprising:
receiving at a data buffer of the FPGA the data representative of the boot code from the serial flash memory; and
monitoring by the FPGA a storage level of the data buffer coupled to receive the data representative of the boot code being accessed from the serial flash memory by the processor.

18. The method of claim 17 , wherein, when a number of words in the data buffer is below a lower range threshold, a plurality of wait commands are issued until the number of words in the data buffer refills to a predefined number of words.

19. The method of claim 18 , wherein, when a number of words in the data buffer is above an upper range threshold, a plurality of halt commands are issued until the number of words in the data buffer is reduced to a predefined number of words.

20. A method comprising:
storing data representative of boot code in serial flash memory;
receiving at a data buffer the data representative of the boot code from the serial flash memory;
booting a processor, coupled to the data buffer, with the data representative of the boot code by using respective logic signals set by the processor to start access to the serial flash memory by pointing to at least one predefined location corresponding to at least one starting address of the data representative of the boot code to be transferred to the processor without using a plurality of address lines to access the serial flash memory; and
monitoring a storage level of the data buffer coupled to receive the data representative of the boot code being accessed from the serial flash memory by the processor.

21. the method of claim 20 , further comprising:
emulating by a field-programmable gate array (FPGA), coupled between the serial flash memory and the processor, a parallel interface by converting a serial data stream comprising the data representative of the boot code received from the serial flash memory to a parallel data stream to effect parallel data transfer over a data bus to the processor, the FPGA comprising the data buffer.

Assignees

• Lockheed Corp

Inventors

• Kelly Linette L
• Burks Carter
• Melendez Steven J

Classifications

• G06F9/445

  Program loading or initiating (bootstrapping G06F9/4401; security arrangements for program loading or initiating G06F21/57) · CPC title

• G06F13/40 Primary

  Bus structure {(for computer networks G06F15/163; for optical bus networks H04B10/25)} · CPC title

• G06F9/4401

  Bootstrapping (security arrangements therefor G06F21/57) · CPC title

• G06F9/4406

  Loading of operating system · CPC title