Field effect transistor with self-adjusting threshold voltage

Patent metadata

Field	Value
Publication number	US-9343587-B2
Application number	US-201313774731-A
Country	US
Kind code	B2
Filing date	Feb 22, 2013
Priority date	Feb 22, 2013
Publication date	May 17, 2016
Grant date	May 17, 2016

Abstract

Methods for forming field effect transistors (FETs) with improved ON/OFF current ratios in addition to short charging times and the resulting devices are disclosed. Embodiments include forming a gate oxide layer above a channel region in a substrate, forming a partial self-adjusting threshold voltage layer above a drain-side end of the gate oxide layer, and forming a gate above the partial self-adjusting threshold voltage layer and the gate oxide layer.

First claim

What is claimed is:

1. A method comprising:
forming a gate oxide layer above a channel region in a substrate;
forming a self-adjusting threshold voltage layer above the gate oxide layer;
forming a dummy gate on the self-adjusting threshold voltage layer;
removing the dummy gate, forming a cavity;
depositing a gate material on side surfaces of the cavity, leaving exposed a middle portion of the self-adjusting threshold voltage layer; and
removing the middle portion of the self-adjusting threshold voltage layer.

2. The method according to claim 1 , further comprising:
forming the self-adjusting threshold voltage layer above a source-side end and a drain-side end of the gate oxide layer.

3. The method according to claim 1 , further comprising:
after forming the dummy gate, forming an inter-layer dielectric (ILD) surrounding the gate oxide layer, the self-adjusting threshold voltage layer, and the dummy gate; and
after removing at least the middle portion of the self-adjusting threshold voltage layer, filling the cavity with gate material to form a gate.

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Tan Shyue Seng
• Toh Eng Huat
• Quek Elgin Kiok Boone

Classifications

• H10D64/693

  the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials · CPC title

• H10D64/689

  having ferroelectric layers · CPC title

• H10D64/111

  Field plates · CPC title

• H10D64/018

  Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title