Wafer scale packaging platform for transceivers

Patent metadata

Field	Value
Publication number	US-9343450-B2
Application number	US-201414276566-A
Country	US
Kind code	B2
Filing date	May 13, 2014
Priority date	May 5, 2011
Publication date	May 17, 2016
Grant date	May 17, 2016

Abstract

A wafer scale implementation of an opto-electronic transceiver assembly process utilizes a silicon wafer as an optical reference plane and platform upon which all necessary optical and electronic components are simultaneously assembled for a plurality of separate transceiver modules. In particular, a silicon wafer is utilized as a “platform” (interposer) upon which all of the components for a multiple number of transceiver modules are mounted or integrated, with the top surface of the silicon interposer used as a reference plane for defining the optical signal path between separate optical components. Indeed, by using a single silicon wafer as the platform for a large number of separate transceiver modules, one is able to use a wafer scale assembly process, as well as optical alignment and testing of these modules.

First claim

We claim:

1. A method for aligning components of a plurality of optical transceiver modules using a silicon interposer wafer as a platform for assembling a plurality of separate transceiver modules, wherein the silicon interposer wafer comprises a silicon planar surface defining an optical reference plane and a plurality of conductive vias formed through the silicon interposer wafer to provide electrical connections to other components, the method comprising:
forming a dielectric layer over the silicon planar surface of the silicon interposer wafer, wherein the dielectric layer is configured to support the placement and interconnection of electrical integrated circuit components associated with the plurality of separate transceiver modules, the dielectric layer further including electrical conductive paths for providing electrical connection between the supported electrical integrated circuit components and selected ones of the conductive vias of the underlying silicon interposer wafer;
patterning and etching the dielectric layer to create a plurality of openings, thereby exposing the silicon planar surface of the silicon interposer wafer at each opening, wherein the plurality of openings are of predetermined sizes and are disposed in predetermined locations, such that placement of the optical components into corresponding openings of the plurality of openings aligns at least two of the optical components and establishes optical signal paths between the aligned optical components along the optical reference plane; and
assembling the plurality of separate transceiver modules on the silicon interposer wafer.

2. The method of claim 1 , wherein the plurality of openings are created using a selective etchant, such that the etching process stops upon exposure of the underlying silicon interposer wafer.

3. A method for assembling an optical transceiver module, the method comprising:
depositing a dielectric layer over a silicon planar surface of a silicon interposer wafer, wherein the silicon planar surface defines an optical reference plane;
forming a plurality of openings through the dielectric layer, thereby exposing the silicon planar surface of the silicon interposer wafer at each opening; and
positioning a plurality of optical components of the optical transceiver module within corresponding openings of the plurality of openings, thereby aligning at least two of the optical components and establishing optical signal paths along the optical reference plane between the aligned optical components.

4. The method of claim 3 , wherein a plurality of optical transceiver modules are formed in a wafer scale assembly using a common silicon interposer wafer.

5. The method of claim 4 , wherein the plurality of openings are formed by patterning and etching the dielectric layer in predetermined areas associated with the placement of the optical components of the plurality of optical transceiver modules formed in the wafer scale assembly.

6. The method of claim 4 , further comprising attaching a lid component to the combination of the silicon interposer wafer and the dielectric layer and disposed over the optical transceiver modules, the lid component configured to include a plurality of chambers associated with the plurality of optical transceiver modules such that each optical transceiver module is separately encapsulated.

7. The method of claim 6 , wherein attaching the lid component comprises bonding the lid component to the combination of the silicon interposer wafer and the dielectric layer.

8. The method of claim 6 , wherein each optical transceiver module as formed includes a sealing layer defining the outline thereof, the sealing layer used to attach an associated portion of the lid component.

9. The method of claim 8 , wherein a bottom surface of the lid component is covered with a material that creates a permanent attachment to the sealing layer when the lid component is attached to the combination of the silicon interposer wafer and dielectric layer.

10. The method of claim 6 , wherein the lid component comprises one of a silicon wafer and a glass wafer.

11. The method of claim 6 , wherein the lid component comprises a metal component.

12. The method of claim 11 , further comprising coupling the lid component to an associated ground plane using a grounding via formed through the dielectric layer and the silicon interposer wafer.

13. The method of claim 12 , wherein the lid component includes an internal compartment within each chamber, the internal compartment for separately encapsulating the optical portion of each optical transceiver module, providing protection from electromagnetic interference.

14. The method of claim 3 , wherein a set of openings formed through the dielectric layer are associated with optical input/output connections for the optical transceiver modules.

15. The method of claim 14 , wherein the set of openings are disposed at an end region of each optical transceiver module location such that an optical connector is capable of accessing the optical components and is aligned with the optical plane reference surface of the silicon interposer wafer.

16. The method of claim 3 , wherein each optical transceiver module includes optical transmitting components including a laser diode, a lens element, and an optical isolator, and the dielectric layer is formed to include openings for the laser diode, lens element, and optical isolator in each region associated with a separate transceiver module, wherein a set of openings for a laser diode, lens element, and optical isolator in each region are formed to provide optical alignment therebetween, with the laser diode disposed in a first opening, the lens element disposed in a second opening, and the optical isolator disposed in a third opening of the dielectric layer.

17. The method of claim 16 , wherein a single lens element is utilized with both transmitting and receiving optical signals, the single lens element comprising a lens array and disposed in an opening in the dielectric layer positioned to align with both the optical transmitting and receiving components.

18. The method of claim 3 , wherein each optical transceiver module includes optical transmitting components including a laser diode, a lens element, an optical isolator, and a submount component, the laser diode, lens element and optical isolator being attached to a surface of the submount component in an aligned configuration, the submount component being disposed within an opening formed through a predetermined area of the dielectric layer.

19. The method of claim 3 , wherein each optical transceiver module includes optical receiving components including a lens element and a photodiode, and the dielectric layer is formed to including openings for the lens element and the photodiode in each region associated with a separate transceiver module, the openings being configured to provide optical alignment between an incoming optical signal, the photodiode and the lens element.

20. A method for aligning components of an optical transceiver module, the method comprising:
positioning a plurality of optical components of the optical transceiver module within a plurality of openings formed through a dielectric layer, thereby aligning at least two of the plurality of optical components and establishing optical signal paths between the aligned optical components along an optical reference plane,
wherein the optical reference plane is defined by a silicon planar surface of a silicon interposer wafer, the dielectric layer i

Assignees

• Cisco Tech Inc

Inventors

• Shastri Kalpendu
• Patel Vipulkumar
• Webster Mark
• Gothoskar Prakash
• Kachru Ravinder
• Pathak Soham
• Yelamarty Rao V
• Daugherty Thomas
• Dama Bipin
• Patel Kaushik
• DESAI Kishor

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• H01L2224/16225

  Electricity · mapped topic

• H01L2224/48227

  Electricity · mapped topic