Stress mitigation structure for wafer warpage reduction

Patent metadata

Field	Value
Publication number	US-9343403-B2
Application number	US-201414483944-A
Country	US
Kind code	B2
Filing date	Sep 11, 2014
Priority date	Apr 4, 2014
Publication date	May 17, 2016
Grant date	May 17, 2016

Abstract

An integrated circuit device includes a substrate. The integrated circuit device also includes a first conductive stack including a back-end-of-line (BEOL) conductive layer at a first elevation with reference to the substrate. The integrated circuit device also includes a second conductive stack including the BEOL conductive layer at a second elevation with reference to the substrate. The second elevation differs from the first elevation.

First claim

What is claimed is:

1. An integrated device comprising:
a substrate supporting a first interlayer dielectric;
a first conductive stack comprising a back-end-of-line (BEOL) conductive layer at a first elevation with reference to the substrate, wherein the first conductive stack comprises a first conductive layer directly on a surface of the substrate, the first interlayer dielectric directly on surfaces of the first conductive layer, a dielectric layer on the first conductive layer, a second conductive layer on the dielectric layer, and a third conductive layer directly on the first interlayer dielectric and coupled to the first conductive layer through a first via as the BEOL conductive layer at the first elevation; and
a second conductive stack comprising the BEOL conductive layer at a second elevation relative to the substrate that differs from the first elevation, wherein the second conductive stack comprises the third conductive layer directly on the surface of the substrate as the BEOL conductive layer at the second elevation.

2. The integrated device of claim 1 , wherein the surface of the substrate is exposed between the first conductive stack and the second conductive stack.

3. The integrated device of claim 1 , comprising an inductor formed with the first conductive layer and the third conductive layer.

4. The integrated device of claim 1 , wherein the first conductive stack comprises a metal-insulator-metal capacitor formed with the first conductive layer, the dielectric layer between the first conductive layer and the second conductive layer, and the second conductive layer.

5. The integrated device of claim 1 incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer.

6. An integrated device comprising:
means for supporting a first interlayer dielectric;
a first conductive stack comprising a back-end-of-line (BEOL) conductive layer at a first elevation with reference to the supporting means, wherein the first conductive stack comprises a first conductive layer directly on a surface of the supporting means, the first interlayer dielectric directly on surfaces of the first conductive layer, a dielectric layer on the first conductive layer, a second conductive layer on the dielectric layer, and a third conductive layer directly on the first interlayer dielectric and coupled to the first conductive layer through a first via as the BEOL conductive layer at the first elevation; and
a second conductive stack comprising the BEOL conductive layer at a second elevation relative to the supporting means that differs from the first elevation, wherein the second conductive stack comprises the third conductive layer directly on the surface of the supporting means as the BEOL conductive layer at the second elevation.

7. The integrated device of claim 6 , wherein the surface of the supporting means is exposed between the first conductive stack and the second conductive stack.

8. The integrated circuit device of claim 6 , comprising an inductor formed with the first conductive layer and the third conductive layer.

9. The integrated device of claim 6 , wherein the first conductive stack comprises a metal-insulator-metal capacitor formed with the first conductive layer, the dielectric layer between the first conductive layer and the second conductive layer, and the second conductive layer.

10. The integrated device of claim 6 incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer.

Assignees

• Qualcomm Inc

Inventors

• Lan Je-Hsiung Jeffrey
• Berdy David Francis
• Zuo Chengjie
• Kim Daeik Daniel
• Yun Changhan Hobie
• Velez Mario Francisco
• Mudakatte Niranjan Sunil
• Mikulka Robert Paul
• Kim Jonghae

Classifications

• H10P14/40

  of conductive or resistive materials · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/496

  Capacitor integral with wiring layers · CPC title

• H10W20/495

  Capacitive arrangements or effects of, or between wiring layers · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title