Semiconductor device, fabricating method thereof and semiconductor package including the semiconductor device

Patent metadata

Field	Value
Publication number	US-9343361-B2
Application number	US-201314072777-A
Country	US
Kind code	B2
Filing date	Nov 5, 2013
Priority date	Nov 29, 2010
Publication date	May 17, 2016
Grant date	May 17, 2016

Abstract

In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, the method comprising:
forming a via hole in a semiconductor substrate;
forming a via hole insulating layer within the via hole;
forming a conductive connector within the via hole to form a through via extending from a first surface of the semiconductor substrate;
thereafter, forming a redistribution trench in a substrate surface of the substrate opposite to the first surface to define a second surface of the substrate, the redistribution trench connected with the via hole;
forming an insulation layer on the second surface including the trench; and
removing a region of the insulation layer to form an insulation layer pattern that defines an opening that exposes a region of the conductive connector, wherein a portion of the insulation layer pattern overlaps a region of the conductive connector.

2. The method of claim 1 , further comprising forming a conductive layer filling the redistribution trench to form a redistribution layer disposed within the redistribution trench.

3. The method of claim 2 , further comprising planarizing the resulting structure including the conductive layer until a top surface of the insulation layer pattern is exposed.

4. The method of claim 3 , wherein planarizing comprises performing chemical-mechanical-polishing (CMP).

5. The method of claim 1 , wherein forming a through via comprises planarizing the resulting structure after forming the conductive connector.

6. The method of claim 1 , further comprising grinding a surface of the substrate opposite to the first surface before forming the redistribution trench to form the substrate surface.

7. The method of claim 1 , wherein the insulation layer pattern is formed while leaving a portion of the insulating layer covering an interface region between the second surface of the substrate and a top surface of the via hole insulating layer.

8. The method of claim 1 , further comprising forming a barrier layer on the via hole insulating layer.

9. The method of claim 1 , further comprising:
forming a protection layer overlying the redistribution layer, the protection layer having an opening part exposing a portion of the redistribution layer; and
forming a conductive bump over the exposed portion of the redistribution layer.

10. The method of claim 1 , wherein a width of the opening that exposes a region of the conductive connector is smaller than a width of the conductive connector.

11. The method of claim 1 , wherein the second surface of the substrate in the redistribution trench is formed to have substantially the same height as an exposed surface of the conductive connector.

12. The method of claim 1 , wherein the second surface of the substrate in the redistribution trench is formed to have a height lower than that of a top surface of the through via so that the through via has an elevated portion rising from the second surface.

13. The method of claim 12 , wherein the insulation layer pattern covers sidewalls of the elevated portion of the through via and a portion of a top surface of the elevated portion of the through via.

14. The method of claim 1 , wherein the redistribution trench is formed above the through via and has a width smaller than a width of the via hole.

15. The method of claim 14 , wherein the insulation layer pattern on a vertical portion of the redistribution trench extends along a portion of the via hole insulating layer.

16. The method of claim 2 , wherein a portion of the redistribution layer is disposed directly on the conductive connector.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Ho-Jin
• Cho Tae-Je
• Jang Dong-Hyeon
• Song Ho-Geon
• Jeong Se-Young
• Kang Un-Byoung
• Yoon Min-Seung

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W72/9226

  with via interconnections · CPC title

• H10W72/07254

  changes in dispositions · CPC title