Semiconductor device and method for manufacturing same

Patent metadata

Field	Value
Publication number	US-9337213-B2
Application number	US-201314389812-A
Country	US
Kind code	B2
Filing date	Mar 29, 2013
Priority date	Apr 4, 2012
Publication date	May 10, 2016
Grant date	May 10, 2016

Abstract

This semiconductor device ( 100 ) includes: a gate electrode ( 3 ); a gate insulating layer ( 4 ); an oxide layer ( 50 ) which is formed on the gate insulating layer ( 4 ) and which includes a first conductor region ( 55 ) and a first semiconductor region ( 51 ) that overlaps at least partially with the gate electrode ( 3 ) with the gate insulating layer ( 4 ) interposed between them; a source electrode ( 6 s ) formed to contact with the upper surface of the first semiconductor region ( 51 ) of the oxide layer ( 50 ); a drain electrode ( 6 d ) which is formed to contact with the upper surface of the first semiconductor region ( 51 ) of the oxide layer ( 50 ) and which is electrically connected to the first conductor region ( 55 ); and a conductive layer ( 60 ) which is formed in contact with the upper surface of the oxide layer ( 50 ) and which a plurality of holes ( 66 ) or notches. The oxide layer ( 50 ) has a plurality of second conductor regions ( 57, 58 ), and each of which has a surface exposed inside respective one of the holes or notches of the conductive layer.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a substrate;
a gate electrode formed on the substrate;
a gate insulating layer formed over the gate electrode;
an oxide layer which is formed on the gate insulating layer and which includes a first semiconductor region and a first conductor region, wherein the first semiconductor region overlaps at least partially with the gate electrode with the gate insulating layer interposed between them;
a source electrode formed to contact with the upper surface of the first semiconductor region of the oxide layer;
a drain electrode which is formed to contact with the upper surface of the first semiconductor region of the oxide layer and which is electrically connected to the first conductor region; and
a conductive layer which is formed to contact with the upper surface of the oxide layer and which has a plurality of holes or notches, wherein
the oxide layer includes a plurality of second conductor regions, and each of which has an upper surface exposed inside respective one of the plurality of holes or notches of the conductive layer;
the conductive layer includes a line, and the line includes at least some of the plurality of holes or notches; and
the semiconductor device further includes an insulating layer covering the conductive layer such that, in the at least some of the plurality of holes or notches of the line, at least some of the plurality of second conductor regions are in direct contact with the insulating layer.

2. The semiconductor device of claim 1 , further comprising a terminal portion,
wherein the conductive layer includes a source connecting layer arranged in the terminal portion, and the source connecting layer has at least some of the plurality of holes or notches, and
the terminal portion includes an external connecting layer which contacts with not only the upper surface of the source connecting layer but also at least some of the plurality of second conductor regions inside the at least some of the holes or notches of the source connecting layer.

3. The semiconductor device of claim 1 , wherein the conductive layer has either a mesh pattern or a striped pattern.

4. The semiconductor device of claim 1 , further comprising a terminal portion,
wherein the oxide layer further includes another conductor region located in the terminal portion, and
the terminal portion includes an external connecting layer which contacts with the upper surface of that another conductor region.

5. The semiconductor device of claim 1 , wherein the conductive layer is formed out of the same conductive film as the source and drain electrodes.

6. The semiconductor device of claim 1 , further comprising:
an upper insulating layer formed over the source and drain electrodes; and
an upper transparent electrode formed on the upper insulating layer,
wherein the upper transparent electrode overlaps at least partially with the first conductor region with the upper insulating layer interposed between them.

7. The semiconductor device of claim 1 , wherein the oxide layer includes In, Ga and Zn.

8. The semiconductor device of claim 1 , wherein the plurality of second conductor regions and the first conductor region are more heavily doped with a dopant than the first semiconductor region is.

9. The semiconductor device of claim 1 , wherein
each of the plurality of holes or notches of the conductive layer has a slit shape, the slit shapes of each of the plurality of holes or notches are arranged in a line to define a single stripe, and adjacent ones of the slit shapes of each of the plurality of holes or notches are spaced apart by an interval of 2 μm to 10 μm.

10. A method for fabricating a semiconductor device, the method comprising the steps of:
(A) providing a substrate having a gate electrode and a gate insulating layer formed on a surface thereof;
(B) forming an oxide semiconductor layer on the gate insulating layer and forming a source electrode, a drain electrode and a conductive layer which contact with the upper surface of the oxide semiconductor layer, the conductive layer having a plurality of holes or notches which expose the upper surface of the oxide semiconductor layer;
(C) forming a protective layer which covers at least a portion of the oxide semiconductor layer to be a channel region; and
(D) forming an oxide layer including a first conductor region, a first semiconductor region including a channel region, and a plurality of second conductor regions by performing a resistance lowering process to lower the resistance of a portion of the oxide semiconductor layer, wherein the first conductor region is formed in a portion of the oxide semiconductor layer which is covered with neither the protective layer nor the conductive layer, the plurality of second conductor regions are formed in portions of the conductive layer which are exposed inside the holes or notches, and the first semiconductor region is formed in a portion of the oxide semiconductor layer that has not had its resistance lowered; wherein
the conductive layer includes a line, and the line includes at least some of the plurality of holes or notches, and in the at least some of the plurality of holes or notches of the line, an insulating layer is formed to cover the conductive layer which contacts at least some of the plurality of second conductor regions.

11. The method of claim 10 , wherein the conductive layer includes a source connecting layer, the source connecting layer has at least some of the plurality of holes or notches, and
the method includes, after the step (D), the step of forming an external connecting layer which contacts with not only the upper surface of the source connecting layer but also at least some of the plurality of second conductor regions.

12. The method of claim 10 , wherein the oxide semiconductor layer includes In, Ga and Zn.

Assignees

• Sharp Kk

Inventors

• ITO Kazuatsu
• Takamaru Yutaka
• Miyamoto Tadayoshi
• Miyamoto Mitsunobu
• Nakazawa Makoto
• Ogawa Yasuyuki
• Uchida Seiichi
• Mori Shigeyasu

Classifications

• H10P14/3434

  being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424) · CPC title

• H10P14/3426

  Oxides · CPC title

• H10P14/412 Primary

  Deposition of metallic or metal-silicide materials · CPC title

• H10W20/096

  by contacting with gases, liquids or plasmas · CPC title

• H10W20/095

  by irradiating with electromagnetic or particle radiation (plasma treatment H10W20/096) · CPC title